A. Akheyar

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Flatband voltage shift of ruthenium gated stacks and its link with the formation of a thin ruthenium oxide layer at the ruthenium/dielectric interface

A systematic study about the flatband voltage (Vfb) shift of Ru gated metal-oxide-semiconductor stacks after thermal treatment in O2 has been performed. The dependence of the Vfb shift on the anneal time and temperature and the thickness of Ru was studied in detail, and a clear link between the Vfb shift and an oxygen diffusion process in Ru was observed. A high temperature thermal treatment of the devices prior to the O2 anneal has no significant impact on the Vfb shift. The Vfb shift is ascribed to the shift of metal gates’ work function, and is not intrinsic to HfO2 gated stacks as similar behavior was also observed on SiO2, from the combination of internal photoemission and conventional capacitance-voltage measurement. No similar Vfb shift was observed for TiN gated stacks and the Vfb shift seems to be more related to the properties of gate electrodes other than those of gate dielectrics. After thermal treatment in O182, from time-of-flight secondary ion mass spectrometry measurement, it was found tha...

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La₂O₃, Dy₂O₃ and Al₂O₃ on both HfSiO(N) and SiO₂ to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

The Impact of Stacked Cap Layers on Effective Work Function With HfSiON and SiON Gate Dielectrics

Cap layers have been used to modulate the effective work function (EWF) for high- /metal-gate CMOS devices. We have investigated the impact of stacking cap layers on the EWF. Stacked cap layers consisting of two sequential cap layers, including, Al₂O₃, Dy₂O₃, Sc₂O₃ and La₂O₃, were formed on HfSiON or SiON as host dielectrics. It is demonstrated that the EWF change due to the stacked cap layers corresponds to the sum of the EWF change from each single cap layer. Furthermore, no host dielectric dependence on the shifts is observed. This behavior is attributed to the complete intermixing of the stacked cap layers with the host dielectrics.

Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

Mechanism of O2-anneal induced Vfb shifts of Ru gated stacks

Abstract A systematic study of the flat-band voltage (Vfb) shift of Ru gated metal-oxide-semiconductor (MOS) capacitors subjected to thermal treatment in O2 has been performed. The dependence of the Vfb shift on the thickness of Ru, anneal temperature and time is studied. The Vfb shift is ascribed to the shift of metal gates’ work function (WF), and is not significantly dependent on the type of dielectric (HfO2 or SiO2). From time-of-flight secondary ion mass spectrometry (TOF-SIMS) measurement, it was found that after thermal treatment in 18O2, 18O penetrated through Ru and was incorporated in the Ru/dielectric interface region. We believe that the formation of the thin interfacial RuOx layer is responsible for the Vfb shift.

Electrical Properties of Low- Metal-Gated n-MOSFETs Using as Interfacial Layer Between HfLaO High- Dielectrics and Si Channel

In this letter, we report that by employing the La₂O₃/SiO_x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta₂C metal-gated n-MOSFETs V_T can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J_G = 10 mA/cm² at 1.1 V), good drive performance (I_on = 900 muA/mum at I_soff = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.

Nitrogen Profile and Dielectric Cap Layer (Al2O3, Dy2O3, La2O3) Engineering on Hf-Silicate

We have investigated Al₂O₃, Dy₂O₃, and La₂O₃ as dielectric cap layers for use in low V_t CMOS integration schemes. The cap layers are found to reduce the V_t by 0.2 V for pFET, and with 0.2 V and 0.5 V for nFET, respectively. Subsequently, we report on the benefits of performing the nitridation (by means of DPN) after cap deposition, instead of before. This allows better control of the nitrogen profile in the stack, resulting in improvement of V_t reduction, V_t wafer uniformity, mobility and BTI characteristics. Finally, we observe that the V_t shift induced by the dielectric cap layer significantly depends on the N-content of the metal gate. After reporting on these three key stack characteristics, we propose two practical single metal CMOS integration schemes.

Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff = 100 nA/μm with VDD = 1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS -0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive are thus offered with 0.94nm EOT. Mechanisms and guidelines for solving theses issues are provided after a comprehensive study here. These concepts are beneficial to either gate-first or gate-last approach with EOT scaling.

Electrical Properties of Low-

In this letter, we report that by employing the La₂O₃/SiO_x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta₂C metal-gated n-MOSFETs V_T can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J_G = 10 mA/cm² at 1.1 V), good drive performance (I_on = 900 muA/mum at I_soff = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.