A. Suhane

Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories

We applied the developed trap spectroscopy by charge injection and sensing to validate the extraction of the silicon nitride trap distribution (both in space and energy) from the modeling of retention transients of charge-trapping memories. We compared three different types of silicon nitrides using these two techniques, and similar distributions were extracted, thus confirming the validity of the charge profiles resulting from the modeling of retention transients and the physics of the proposed model, based on two main mechanisms of charge loss: Poole-Frenkel emission (dominating at high temperature) and direct tunneling (dominating at room temperature).

Electron Trap Profiling Near

The goal of this letter is to investigate and characterize the defects at the Al2O3/gate interface in TANOS memory stacks. To this purpose, gate-side trap spectroscopy by charge injection and sensing is applied on devices featuring different metal gates and different postdeposition anneals. The results show that a high concentration of defect is present in crystalline samples with a TaN or TiN gate.

\hbox{Al}_{2} \hbox{O}_{3}

A statistical evaluation of current-voltage characteristics in small-size vertical poly-Si channels is used to study the poly-Si conduction properties and defects. Three poly-Si process options are considered. It is shown how defects and grain boundaries lead to percolation current paths, modulated by electron charging. Low mobility in microcrystalline-Si can be exchanged for higher mobility in large-grain poly-Si, at the expense of larger variability.

/Gate Interface in TANOS Stack Using Gate-Side Trap Spectroscopy by Charge Injection and Sensing

We present carrier separation experiments based on direct charge measurement to assess the contributions of electrons and holes to the erase transient of TANOS-like nonvolatile memories. The role of different carrier species is analyzed as a function of erase voltage and charge configuration at the initial programmed state. We extend the analysis to band-engineered tunneling barriers, demonstrating that the performance improvement in these devices lies more on the enhancement of hole current rather than that of the electron one.

Statistical characterization of current paths in narrow poly-Si channels

A characterization technique capable of measuring the electrical charge injected during programming operations in silicon nitride based charge trapping memories has been developed. The trapping efficiency, defined as the fraction of carriers which gets trapped in the device with respect to the total injected charge, is extracted and is evaluated along the programming transient for a wide set of devices, featuring different material deposition techniques and different thicknesses. The trapping efficiency is found to be almost insensitive to the injection conditions, whereas it depends on the quantity of filled traps, the thickness of the trapping layer and the conduction band offset between the trapping layer and the top oxide. A higher trapping efficiency in general leads to faster programming transients and more effective programming when increasing the gate voltage.

Experimental Assessment of Electrons and Holes in Erase Transient of TANOS and TANVaS Memories

Rare-Earth aluminates GdAlO and LuAlO are investigated as blocking dielectric for Al2O3 replacement in TANOS flash memory devices. Since the energy bandgap of aluminates strongly depends on their crystallization phase and it is the highest for orthorombic phase, both materials were engineered using templates to assure the highest Eg and k-value after crystallization. As a consequence, the memory stack performances are significantly improved. Compared to Al2O3 reference top dielectric, retention can be improved.

Experimental evaluation of trapping efficiency in silicon nitride based charge trapping memories

In TANOS memory, deeper erase is pursued by implementing a high work function (p-type) metal gate. Our experiments show that the metal gate may also change program and retention in a way that cannot be explained by simple electrostatic considerations. Instead, we suggest that some metal gates may give rise to a change in the properties of the underlying blocking dielectric or the interface with the nitride, leading to the abovementioned observations. Hydrogen appears to be involved in this process.

Optimization of the crystallization phase of Rare-Earth aluminates For blocking dielectric application in TANOS type flash memories

The integration of La, Gd, and Lu aluminates in a Charge-Trapping Flash (CTF) memory flow as alternative trapping materials is evaluated. It is found that, in order to control the mixing of the aluminates with the tunnel oxide, nitride (for Gd) or nitride + oxide (for La and Lu) buffer layers have to be used. It is also found that during the post-deposition annealing treatments, the nitride buffer layer mixes with the tunnel oxide. This results in very good erase and endurance performance, which is attributed to enhanced hole tunneling from the Si substrate.