E. Capogreco

Laser thermal anneal of polysilicon channel to boost 3D memory performance

We have demonstrated that the engineering of Si channel grains in vertical 3D devices is of tremendous importance for read current, leading to up to 10 times higher ID, 3 times steeper STS slope, tighter ID and STS distributions, better channel-oxide interface, less defective grain boundaries and larger memory window. LTA arises as a potential candidate to engineer the Si channel microstructure. The limitations of LTA regarding crystallization depth can be overcome through complementary techniques such as substrate heating assisted LTA. This learning is crucial for the successful fabrication of advanced vertical devices stacks.

Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model

The characterization of vertical poly-Si transistors, important for optimizing vertical SONOS memory configurations, is studied by means of a resistive network model. The statistical variation of the ISD-VG characteristics allows to extract the poly-Si grain size and from the sub-threshold regime information on the energy distribution of the poly-Si defects is extracted. This model indicates the separated impact of interface states and poly-Si states on current and Vth.

MOVPE In1−xGaxAs high mobility channel for 3-D NAND memory

Epitaxially grown In_1-xGa_xAs is integrated for the first time as replacement of polycrystalline silicon (Si) channel down to 45 nm diameter for 3-D NAND memory application. Channels with different compositions are obtained after careful surface preparation by tuning growth conditions such as: temperature, choice of precursors and flow ratio. In_1-xGa_xAs shows superior conduction properties than poly-Si channel: higher I_on and transconductance (g_m). Potentially good memory operations are also found.

Analysis of performance/variability trade-off in Macaroni-type 3-D NAND memory

Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by Laser Thermal Anneal treatment of Macaroni channel.

Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications

Epitaxially grown Si and Si0.6Ge0.4 are integrated as replacement of poly-Si channel in vertical cylindrical transistors for vertical NAND memory application, in order to investigate the impact of the grain boundaries on current conduction. Epi-Si outperforms both poly-Si and Epi-SiGe channels, resulting in the best conduction, with large improvement on both sub threshold swing and transconductance (gm). The experimentally observed gm bimodal distribution for epi Si is corroborated and explained through a resistive network model: lower gm conduction occurs when current needs to cross a high resistance boundary, whereas higher gm is obtained when this boundary is not present.

Feasibility of In x Ga 1– x As High Mobility Channel for 3-D NAND Memory

Epitaxial In_xGa_1-xAs is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate In_xGa_1-xAs are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. In_xGa_1-xAs channels with a diameter down to ~45 nm and different In concentrations are obtained after using two alternative surface preparation routes: HCl and Cl₂. Thanks to the lower thermal budget involved, Cl₂ seems the most suitable route to preserve the thickness of the TuOx. In_xGa_1-xAs channels with In concentration, x, higher than 0.45 have superior conduction properties compared with poly-Si channel, showing higher ION and transconductance.

Direct three-dimensional observation of the conduction in poly-Si and In 1−x Ga x As 3D NAND vertical channels

Nanoscopic details of the conduction in 3D NAND vertical channels are unraveled by a novel slice-and-view tomographic technique, Scalpel SPM. The structural and electrical properties of poly-Si and single crystalline In1-xGaxAs of 45 nm channel diameters are explored/revealed. The impact of the grain boundaries (GBs) in poly-Si and of the material segregation in In1-xGaxAs are shown, thus providing a direct correlation between the channel materials and the electrical performance of the device.

Channel and near channel defects characterization in vertical InxGa1-xAs high mobility channels for future 3D NAND memory

In this paper, we present a first characterization of the charge trapping in vertical 3D SONOS with InxGa1-xAs channel using IV hysteresis and RTN measurements. We show that III-V devices have a high density of border traps leading to an important variability of its electrical parameters. Finally, individual trap analysis show that the III-V devices also possess traps in the channel region and their behavior are similar to the one measured in standard silicon technology.