A. Ivankovic

Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology

This work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration.

3D stacking induced mechanical stress effects

In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

Analysis of microbump induced stress effects in 3D stacked IC technologies

Besides the stress around Cu TSVs, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

FET arrays as CPI sensors for 3D stacking and packaging characterization

FET arrays are investigated from the viewpoint of Chip-Package Interaction (CPI) sensor suitability and presented as a possible solution for experimental characterization of CPI effects during 3D assembly steps: Stacking and packaging. The study presents a methodology consisting of an experimental approach with the support of FEM modeling. The use of the transistors as stress sensors covering in-plane stress components is justified, after which the applicability of the transistors to the actual stacking and packaging stress states is discussed. Calibration to in-plane stress of long and short channel transistors, p and n type, is performed to obtain sensor sensitivities and link stress to current shift by according calculated piezocoefficients. Testing the FET arrays as sensors is firstly done by means of a simple structure where a die is glued to a plastic substrate. The electrical measurements are compared to FEM models and profilometric scans. The sensors are next utilized to obtain first results from 3D stacking and packaging. The underfill - microbump mechanism in a 2-die stack is quantified and initial results on overmould impact are discussed.

Chip package interaction (CPI): Thermo mechanical challenges in 3D technologies

The residual stresses generated during different processing steps and during thermal cycling of 3D stack packages, mimicking its service life, are quantified by Finite Element Modeling (FEM) together with measurements of dedicated FET arrays used as CPI sensors. Thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The test vehicle used in this work is an imecs proprietary logic CMOS IC on top of which a commercial DRAM is stacked. Different test structures contained in the chip, allow monitoring thermo-mechanical stresses and electrical characteristics of TSVs and micro-bumps. It is shown that FET current shifts can be used to measure the stress in the surface of the chip. The use of standard FEM approach is insufficient to simulate the CPI due to the large dimensional difference between the packaging and interconnects structures. Due to size and speed limitations of commercial computers, a 3D thermo mechanical model of a 3D package cannot contain all the details from the package and at the same time simulate the small structures such as metal and dielectric layers in the BEOL. For this reason, multi-scale simulations are the best choice for identifying the critical regions of the package where high stresses and/or delamination failures are expected to occur. We have shown the methodology to follow to study the CPI.

Thermo-mechanical impact of the underfill-microbump interaction in 3D stacked integrated circuits

This paper focuses on stress generated in Si dies as a consequence of the interaction mechanism of the underfill material and microbumps in 3D stacked integrated circuits (ICs). The impact of the mechanism is simulated by means of finite element modeling (FEM) and verified by electrical measurements. Furthermore, a FEM study is employed in order to provide proposals for stress reduction in the active Si area due to stacking. In result, guidelines for the choice of underfill material and critical dimensional parameters of 3D stacks are pointed out.

Reliability concerns in copper TSV's: Methods and results

Due to their large volume and close proximity to devices, the reliability of copper TSVs is a concern, both with respect to mechanical stresses induced by the TSV in the Si and with respect to copper drift into the liner and the Si. This abstract summarizes recent achievements obtained in imecs 3D-reliability work package where above mentioned reliability concerns are evaluated in detail. To study the impact of mechanical stresses induced by the TSV in the Si, the saturation drain currents Id of transistors have been used as stress sensors. The offset of the Id of transistors closer to a TSV with respect to transistors far away from a TSV has been studied, both directly after processing and after thermal storage and thermal shock. It is shown that stresses generated by the TSV in the Si increase after thermal storage above certain temperatures while thermal shock reduces these stresses. The first is attributed to stress relaxation at high temperatures, while the latter is attributed to cracking/delamination at critical interfaces. To study continuity in TSV-barriers, a method, further referred to as dual ramp rate IVctrl, is introduced. The method consists of controlled current-voltage sweeps at different rates. The difference in breakdown fields for different ramp rates allows estimating TDDB (=Time Dependent Dielectric Breakdown) field acceleration parameters. Applying a negative voltage to the TSV (-V) does not allow copper to drift into the liner, while when applying a positive voltage (+V) to the TSV, copper can drift into the liner in case of a defective, non-continuous barrier. Comparing TDDB field acceleration parameters of -V versus +V tests gives insight in barrier properties. In our study, weak reliability is observed in systems where the TSV-barriers are not continuous.

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

The 3D IC stacking technology with Through Silicon via (TSV) approach promises lower cost, smaller footprint and higher performance for heterogeneous system integration. 3D integration technology needs key components to be enabled: Like TSV technology, Wafer thinning, thin wafer carrier and handling technology and μbumps interconnects. In the via-middle 3D-Stacked IC approach, Cu filled TSVs are integrated after device fabrication and before metal 1. The stress patterns around TSVs and μbumps are considered as important concerns for 3D integration, as this leads to additional variability in MOSFET mobility, threshold voltage, and drivability. This contribution reviews the assessment of TSV and μbumps proximity effects on FEOL device performance.

Development of B-spline X-ray Diffraction Imaging techniques for die warpage and stress monitoring inside fully encapsulated packaged chips

Advanced packaging is a key “More than Moore” (MtM) enabling technology [1]. In all of these advanced packaging processes the semiconductor die are becoming much thinner (e.g. 25-50 μm thick) and many packages include multiply stacked silicon die. This leads to very thin packages where there is a trade-off between the thickness of constituent package layers and their rigidity, thus leading to reliability problems. Currently there are no compelling metrologies that can non-destructively measure the stress and/or warpage of the semiconductor die inside these packaged chips. Furthermore, since the thermal processing of these packages leads to the generation of thermal/mechanical stresses a new metrology, which is capable of real-time, or near real-time, monitoring of the generation or amelioration of these stresses during the thermal processing, would be a major advantage. In this study, we report on recent advances in the development of a new technique, which we describe as B-Spline X-Ray Diffraction Imaging (B-XRDI), which produces a reconstruction of strain field and/or lattice misorientation data from x-ray diffraction data/images of the in situ semiconductor die inside a test wirebonded encapsulated BGA package. High-speed digital x-ray topography images are captured at a synchrotron source (ANKA, Germany and Diamond, UK) in times as short as 8 seconds for a full 8 mm × 8 mm semiconductor die inside the fully encapsulated packages. Using a laboratory-based source (Jordan Valley Bede D1 High Resolution X-Ray Diffractometer) and applying the B-Spline technique, maps are also produced of the entire silicon die, which reveal warpage via measurements of x-ray rocking curve full-widths-at-half-maximum (FWHM) as a function of position across the encapsulated packages. These maps are also correlated with warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM).