Akihito Tanabe

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

Influence of Fermi‐level pinning on barrier height inhomogeneity in PtSi/p‐Si Schottky contacts

The barrier height inhomogeneity in PtSi/p‐Si and IrSi/p‐Si was observed by internal photoemission. New Fowler equations were introduced, to analyze the observed properties. Two regions with different barrier heights were assumed to coexist, and the individual barrier heights were evaluated. One of two barrier heights was consistent with the generally obtained value in individual contacts. The other was 0.39 eV in both contacts. The origin of two regions was explained in terms of Fermi‐level pinning.

Performance enhancement of partially and fully depleted strained-SOI MOSFETs

The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicon-germanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained-SOI MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70-nm-gate-length strained-SOI n-MOSFETs. Fully depleted strained-SOI MOSFETs with back gate were successfully fabricated on SGOI substrate with SiGe layers as thin as 25 nm. The back-gate bias control successfully operated and the higher current drive was obtained by a combination of the low doping channel and the back-gate control.

A 1/4 inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode

A newly developed 1/4-inch 380 k pixel IT-CCD image sensor features a novel cell structure in which signal charges are read out from a photodiode (PD) to a vertical-CCD (V-CCD) in a gate-assisted punchthrough mode. The cell structure, fabricated through the use of high energy ion implantation technology, enables both deep PD formation and transfer-gate (TG)/channel-stop (CS) length reduction. Deep PD formation helps increase sensitivity per PD unit area, and TG/CS length reduction widens both PD and V-CCD areas. Although the cell size is small (4.8 /spl mu/m (H)/spl times/5.6 /spl mu/m (V)), the sensor achieves both high sensitivity (35 mV/lx) and a high saturation signal (600 mV). >

A standard-television compatible 648*487 pixel Schottky-barrier infrared CCD image sensor

Describes a 648*487 pixel PtSi Schottky-barrier infrared CCD image sensor. Due to the development of the modified inverted-LOCOS process, which can minimize dead regions, and the two-dopant concentration structure, which achieves both a large charge capability and high transfer efficiency, a 40% fill factor in a 21- mu m*21- mu m pixel and a 0.1-K noise equivalent temperature difference were obtained. >

A 1/2-in 1.3 M-pixel progressive-scan IT-CCD for digital still camera applications

A 1/2-in 1.3 M-pixel progressive-scan interline-transfer charge-coupled-device (IT-CCD) image sensor has been developed for small, low-power mega-pixel digital still cameras (DSCs). The pixel size as small as 5 /spl mu/m square makes small-size progressive-scan IT-CCD (8.3/spl times/7.1 mm/sup 2/) for the SXGA format. A two-phase-drive horizontal-CCD with phosphorus-implanted storage regions helps reduce the driving voltage to 2.5 V, resulting in the power consumption of the device being as low as 146 mW. A new source-follower amplifier with separate p-well driver transistors achieves 12% higher gain than that obtained using a conventional amplifier. An overflow drain with a self-adjusting potential barrier can instantly remove superfluous charges in vertical-CCDs just before an exposure period, which enables DSCs to perform such functions as quick auto-focusing and dark-current removal. New dual operation modes for still and motion pictures can provide not only high-resolution color signals in a 15-frame/s 1050-line progressive mode but also wide-dynamic-range color signals in a 30-frame/s 525-line progressive mode. The latter mode employs a pixel-exchange-and-mix readout operation that helps halve the number of scanning lines with no loss in sensitivity and color information.

Device characterizations and physical models of strained-Si channel CMOS

Recent progress on the development of strained-Si CMOS is reviewed with emphasis on the electrical properties. The device parameters extracted from strained-Si CMOS and the physical models, indispensable in describing the electrical characteristics, are presented. In addition, new requirements for device characterization, specific to strained-Si devices, which include V/sub th/ control and influence of Ge, are also addressed.

A silicon homojunction infrared detector having an active metal film on an n/sup ++/ layer

A silicon n/sup ++/pn homojunction infrared detector, in which a degenerate n/sup ++/ layer is backed by a metal film forming an ohmic contact, has been proposed and studied. The metal film is a photoelectric conversion region along with the n/sup ++/ layer. Although, for an n/sup ++/pn detector without the metal film, very poor rectifying properties are observed when the n/sup ++/ layer thickness is extremely reduced, the new detector, employing a thin PtSi film as the metal film, shows normal diode I-V characteristics, since the PtSi film provides increased surface conductivity. The new detector has achieved an increase in operatable temperature, or an extension of cutoff wavelength, and operated with cutoff wavelengths of 11.9 /spl mu/m, 18.7 /spl mu/m and about 30 /spl mu/m at 70 K, 50 K, and 30 K, respectively, because the saturation current density for the new detector has been reduced to about one tenth that for the previously reported n/sup ++/pn detector. The responsivity for the new detector has increased to 1.1-3.8 times as large as that for the previously reported n/sup ++/pn detector, when both detectors have the same cutoff wavelength. >

High fill factor and progressive scan PtSi Schottky-barrier IR-CCD image sensor having new wiring structure over photodiodes

A back surface illuminated 130/spl times/130 pixel PtSi Schottky-barrier (SB) IR-CCD image sensor has been developed by using a new wiring structure, referred to as CLOSE Wiring. CLOSE Wiring, designed to effectively utilize the space over the SB photodiodes, brings about flexibility in clock line designing, high fill factor, and large charge handling capability in a vertical CCD (VCCD). This image sensor uses a progressive scanned interline-scheme, and has a 64.4 percent fill factor and 3.3 /spl mu/m wide VCCD in a 30 /spl mu/m/spl square/ pixel. The charge handling capability for VCCD achieves 9.8/spl times/10/sup 5/ electrons. The noise equivalent temperature difference obtained was 0.099 K for operation at 120 frames/sec with f/1.3 optics.<<ETX>>

Strained-Si/SiGe-on-insulator wafers fabricated by Ge-condensation process

This work presents successful fabrication of uniform 150 and 200 mm strained-Si/SiGe-on-insulator wafers by using the Ge-condensation process and discusses some integration issues. Epitaxial growth of both SiGe and Si films was performed at 600 /spl deg/C in 1 Pa by a mixture of SiH/sub 4/, GeH/sub 4/, and H/sub 2/ using LPCVD system with vertical reactor type. CMOS devices were also fabricated to examine the material quality of the 150 and 200 mm SSOI wafers and commercially available SOI. Poly-Si gate CMOS process with 10 nm thick gate oxide was employed in this work.