Shu Nakaharai

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique

A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobilit...

Quantitative Raman Spectrum and Reliable Thickness Identification for Atomic Layers on Insulating Substrates

We demonstrate the possibility in quantifying the Raman intensities for both specimen and substrate layers in a common stacked experimental configuration and, consequently, propose a general and rapid thickness identification technique for atomic-scale layers on dielectric substrates. Unprecedentedly wide-range Raman data for atomically flat MoS(2) flakes are collected to compare with theoretical models. We reveal that all intensity features can be accurately captured when including optical interference effect. Surprisingly, we find that even freely suspended chalcogenide few-layer flakes have a stronger Raman response than that from the bulk phase. Importantly, despite the oscillating intensity of specimen spectrum versus thickness, the substrate weighted spectral intensity becomes monotonic. Combined with its sensitivity to specimen thickness, we suggest this quantity can be used to rapidly determine the accurate thickness for atomic layers.

Ambipolar MoTe2 transistors and their applications in logic circuits.

We report ambipolar charge transport in α-molybdenum ditelluride (MoTe2 ) flakes, whereby the temperature dependence of the electrical characteristics was systematically analyzed. The ambipolarity of the charge transport originated from the formation of Schottky barriers at the metal/MoTe2 contacts. The Schottky barrier heights as well as the current on/off ratio could be modified by modulating the electrostatic fields of the back-gate voltage (Vbg) and drain-source voltage (Vds). Using these ambipolar MoTe2 transistors we fabricated complementary inverters and amplifiers, demonstrating their feasibility for future digital and analog circuit applications.

Thickness-Dependent Interfacial Coulomb Scattering in Atomically Thin Field-Effect Transistors

Two-dimensional semiconductors are structurally ideal channel materials for the ultimate atomic electronics after silicon era. A long-standing puzzle is the low carrier mobility (μ) in them as compared with corresponding bulk structures, which constitutes the main hurdle for realizing high-performance devices. To address this issue, we perform a combined experimental and theoretical study on atomically thin MoS2 field effect transistors with varying the number of MoS2 layers (NLs). Experimentally, an intimate μ-NL relation is observed with a 10-fold degradation in μ for extremely thinned monolayer channels. To accurately describe the carrier scattering process and shed light on the origin of the thinning-induced mobility degradation, a generalized Coulomb scattering model is developed with strictly considering device configurative conditions, that is, asymmetric dielectric environments and lopsided carrier distribution. We reveal that the carrier scattering from interfacial Coulomb impurities (e.g., chemical residues, gaseous adsorbates, and surface dangling bonds) is greatly intensified in extremely thinned channels, resulting from shortened interaction distance between impurities and carriers. Such a pronounced factor may surpass lattice phonons and serve as dominant scatterers. This understanding offers new insight into the thickness induced scattering intensity, highlights the critical role of surface quality in electrical transport, and would lead to rational performance improvement strategies for future atomic electronics.

High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

A new approach to form strained SiGe-on-insulator (SGOI) channel transistors, allowing fabrication of MOSFETs with very high Ge fraction in selected areas on a silicon-on-insulator substrate, is demonstrated. This method consists of epitaxial growth of an SiGe layer with a low Ge fraction and local oxidation processes. An obtained SGOI pMOSFET with a Ge fraction of 0.93 exhibits up to a tenfold enhancement in mobility. It is also found that MOSFETs having strained SGOI channels with thicknesses of less than 5 nm exhibit hole-mobility enhancement factors of over two. These results indicate that the local SGOI channels fabricated by the proposed technique are promising for implementation of high-mobility SiGe or Ge-channel MOSFETs in system-on-chip (SoC) devices.

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

[110]-surface strained-SOI CMOS devices

We have newly developed [110]-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on [110]-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on [110]-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of [110]-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of [110]-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of [110]-surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the [110]-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a [110]-surface Si. As a result, the [110]-surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS.

Thickness scaling effect on interfacial barrier and electrical contact to two-dimensional MoS2 layers.

Understanding the interfacial electrical properties between metallic electrodes and low-dimensional semiconductors is essential for both fundamental science and practical applications. Here we report the observation of thickness reduction induced crossover of electrical contact at Au/MoS2 interfaces. For MoS2 thicker than 5 layers, the contact resistivity slightly decreases with reducing MoS2 thickness. By contrast, the contact resistivity sharply increases with reducing MoS2 thickness below 5 layers, mainly governed by the quantum confinement effect. We find that the interfacial potential barrier can be finely tailored from 0.3 to 0.6 eV by merely varying MoS2 thickness. A full evolution diagram of energy level alignment is also drawn to elucidate the thickness scaling effect. The finding of tailoring interfacial properties with channel thickness represents a useful approach controlling the metal/semiconductor interfaces which may result in conceptually innovative functionalities.