Norio Hirashita

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Effects of surface hydrogen on the air oxidation at room temperature of HF-treated Si(100) surfaces

Thermally stimulated desorption and x‐ray photoelectron spectroscopy were used to study the air oxidation at room temperature of HF‐treated Si(100) surfaces. The desorption results indicated an appreciable density of hydrogen at the surface. Air oxidation experiments with predesorbing surface hydrogen were carried out and an obtained linear relationship between the amount of H2 desorption and oxidation indicated that the oxidation was allowed by H2 desorption. The surface hydrogen was also found to be stable in air at room temperature and to contribute to a retardation in air oxidation of the surface.

Thermal desorption and infrared studies of plasma-enhanced chemical vapor deposited SiO films with tetraethylorthosilicate

Thermal desorption and Fourier transform infrared spectroscopies were used to study plasma-enhanced chemical vapor deposited SiO films from tetraethylorthosilicate. Significant water desorption and concomitant structural changes were observed for the films during subsequent heat treatments between 100 and 700°C. The films exhibited three distinct water desorption states. The desorption temperatures were approximately 100-200°C for the first state, 150-300°C for the second state, and 350-650°C for the third state. Air exposure experiments revealed that the first and second states resulted from absorbed water and the third state from constitution water. The first and second desorption states were confirmed to originate from liquid like water and water molecules hydrogen-bonded to Si-OH bonds at macropore sites in the films, respectively. The third desorption state was found to result from Si-OH bonds formed during the film growth. This desorption of constitution water was considered to be accompanied by a microstructural change of the films.

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

High-Performance Uniaxially Strained SiGe-on-Insulator pMOSFETs Fabricated by Lateral-Strain-Relaxation Technique

Novel uniaxially strained SiGe-on-insulator (SGOI) pMOSFETs with Ge content of 20% have been successfully fabricated by utilizing lateral (uniaxial) strain-relaxation process on globally (biaxially) strained SGOI substrates. Drastic increase of drain current (80%) caused by the change of strain from biaxial to uniaxial and the mobility enhancement of about 100% against the control Si-on-insulator pMOSFETs are observed in SGOI pMOSFET. This high mobility enhancement is maintained in high vertical effective fields as well as in short-channel devices. As a result, significant ION enhancement of 80% is demonstrated in 40-nm gate-length uniaxially strained SGOI pMOSFET

Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Electrical properties of Ge-rich SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures fabricated by Ge condensation process have been studied. The SGOI and GOI structures for Ge composition, xGe, larger than 0.4 exhibit p-type conduction. The hole density is found to rapidly increase from 1016 to 1018 cm-3 with an increase in xGe during the Ge condensation and to decrease down to low-1017 cm-3 when xGe reaches unity. Analyses of scanning spreading resistance microscopy have directly revealed that the SGOI and GOI structures are highly conductive along the crosshatched slip bands formed during the condensation, meaning that the holes are induced along the slip bands in SGOI and GOI films. As a result, it is concluded that the hole induced during the Ge condensation is strongly associated with the slip band formation.

Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique

Formation process of Ge-on-insulator (GOI) layers by Ge condensation with very high purity of Ge is clarified in terms of diffusion behaviors of Si and Ge in a SiGe layer. It is shown that the diffusion behavior affects the Ge condensation process, and the purity of GOI layer can be determined by the relation between oxidation and diffusion of Si. Experimental results support a model of GOI formation that the selective oxidation of Si in SiGe continues until the formation of a GOI layer with the residual Si fraction of less than 0.01%. Based on this model, we quantitatively clarify the reason why GOI layers can reach very low residual Si fraction without oxidizing Ge by calculating the diffusion behavior of Si during the Ge condensation process. As a result, we have found that the thermal diffusion of Si is sufficiently fast so that the selective oxidation of Si can continue during the GOI formation process until the averaged residual Si fraction in the SGOI layer becomes lower than 0.03%, which is essent...

Strain analysis in ultrathin SiGe-on-insulator layers formed from strained Si-on-insulator substrates by Ge-condensation process

Ultrathin strained SiGe-on-insulator (sSGOI) layers were fabricated by Ge condensation, in which Si1−xGex layers on strained Si-on-insulator (sSOI) substrates were oxidized, and their strain and defects were investigated. With increasing the Ge fraction x, the compressive strain in the SGOI layers was found to linearly increase up to ∼2%. The linear strain dependence on x was offset by the preexisting tensile strain in the sSOI substrate compared to that of conventional SGOI layers formed on unstrained SOI substrates. As a result, pseudomorphic sSGOI layers were obtained on the sSOI substrate up to higher x (∼0.75) than on a SOI substrate.

Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parameters

This paper demonstrates the successful fabrication of strained-SOI MOSFETs using SiGe on insulator (SGOI) substrates. 200mm SGOI wafer with Ge content of 30% is fabricated by Ge condensation technique. The performance enhancement over 14% is obtained in gate length of 70 nm. Furthermore, fully-depleted strained-SOI MOSFETs with back gate is demonstrated. Thin strained-Si layer can suppress the abnormal off leakage current due to the enhancement impurity diffusion.

Physical Understanding of Strain-Induced Modulation of Gate Oxide Reliability in MOSFETs

We have systematically investigated the effects of strain on the gate oxide reliability, using biaxially strained Si MOSFETs, to elucidate their physical origins. It was found that the time-dependent dielectric breakdown reliability was significantly improved in strained Si nMOSFETs but was slightly degraded in strained Si pMOSFETs. These observations could be well explained by the strain-induced modulation of the gate current, resulting from band-structure modulation in the channels. It was also found that negative bias temperature instability was degraded in the strained Si pMOSFETs. This fact was attributable to the strain-induced enhancement of hole tunneling probability and hole wave function penetration into Si-H bonding states near the MOS interface, which could enhance Si-H bond breaking.