Alain Phommahaxay

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This has been successfully demonstrated for the first time in a 300mm production line, and the compatibility of thin wafer handling with backside processing has been evaluated.

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding has become a key element in device processing over the past years. Today, although solutions for wafer support systems have made great progress in terms of process performance, thin wafer debonding and handling remains extremely challenging. Our motivation to move away from thermoplastic high temperature melt debonding materials to room temperature debondable materials is clearly exposed in this paper: we describe the process integration and manufacturing aspects of the Brewer Science® ZoneBOND® temporary bonding process, as a one-to-one alternative to the Brewer Science® WaferBOND® HT-10.10 slide debonding material. Process issues related to the material integration into complex 3D flows as well as key learnings are described in details. One important modification that was required is related to the edge-trimming process that is typically performed on the active device wafer prior to bonding and grinding. The ZoneBOND® material was found not to be compatible with this process, resulting in permanent defects and damages during grinding. To resolve this issue, the process flow was modified to an edge-trimming after wafer bonding approach. Finally, the room temperature debonding process is fully described.

Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding

In this paper we report on the use of Silicon wafer to wafer bonding technology using Trough Silicon Vias (TSV) and Cu to Cu hybrid interconnects. We demonstrate that multiple wiring levels of two separate wafers, can be interconnected on a full wafer scale by means of wafer bonding using classical metallization schemes found in ICs such as Al and Cu interconnect technologies. The wafer to wafer stacking is accomplished by back to face aligned wafer bonding using a combination of polymer bonding and copper to copper thermo-compression bonding. The Cu TSV-last process is inserted after the integration of a classical Al interconnect scheme. The top wafer is thinned down to 25μm and bonded to the landing wafer by hybrid Cu-Cu bonding in a high force bonding tool. Measurements of TSV interconnect chain structures covering the full wafer surface are provided as a demonstration of the relevance of such a process route.

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications

Thin wafer handling has become a very challenging topic of emerging 3D technologies, and temporary wafer bonding to a carrier support wafer is one way to guarantee the required mechanical stability and rigidity to the thin wafer during subsequent backside processing. The temporary bonding approach followed by Imec is based on the adhesive material HT10.10 from Brewer Science (WaferBond® HT-10.10). The thermal and chemical stability of the temporary adhesive layer has been fully assessed and characterized in a 300mm production line, and for the first time we report on the full integration of thin wafer handling with backside processing on 300mm CMOS wafers.

High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias

Among the technological developments pushed by the emergence of 3D-ICs, Through Silicon Via (TSV) technology has become a standard element in device processing over the past years. As volume increases, defect detection in the overall TSV formation sequence is becoming a major element of focus nowadays. Robust methods for in-line void detection during TSV processing are therefore needed especially for scaled down dimensions. Within this framework, the current contribution describes the successful application of innovative GHz Scanning Acoustic Microscopy (SAM) to TSV void detection in a via-middle approach.

Metrology and inspection challenges for manufacturing 3D stacked IC's

In this paper we discuss the numerous metrology and inspection challenges that need to be overcome to really have high volume manufacturing of 3D integrated chips. The key metrology and inspections issues are addressed module wise. We start with the TSV module then move on to the wafer bonding and thinning module. This is followed by the bumping module, de-bonding module and finally we finish with the stacking module. Within each of the modules we show the possible solutions for metrology and inspection and also discuss limitations of the available metrology and inspection if it is warranted.

Process characterization of thin wafer debonding with thermoplastic materials

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on extensive characterization of a thermal debonding approach to answer these challenges.

Evolution of temporary wafer (de)bonding technology towards low temperature processes for enhanced 3D integration

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, wafer thinning has become a key element in device processing over the past years. One major criteria, being Total Thickness Variation after thinning, various aspects in the temporary bonding step will be discussed with this respect. While these elements are now becoming mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging and are still prone for evolution.