Greet Verbinnen

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding has become a key element in device processing over the past years. Today, although solutions for wafer support systems have made great progress in terms of process performance, thin wafer debonding and handling remains extremely challenging. Our motivation to move away from thermoplastic high temperature melt debonding materials to room temperature debondable materials is clearly exposed in this paper: we describe the process integration and manufacturing aspects of the Brewer Science® ZoneBOND® temporary bonding process, as a one-to-one alternative to the Brewer Science® WaferBOND® HT-10.10 slide debonding material. Process issues related to the material integration into complex 3D flows as well as key learnings are described in details. One important modification that was required is related to the edge-trimming process that is typically performed on the active device wafer prior to bonding and grinding. The ZoneBOND® material was found not to be compatible with this process, resulting in permanent defects and damages during grinding. To resolve this issue, the process flow was modified to an edge-trimming after wafer bonding approach. Finally, the room temperature debonding process is fully described.

TSV metrology and inspection challenges

The interest in 3D packaging and specifically TSV processes has grown significantly in the past few years, with nearly every major chip manufacturer announcing plans to develop and implement this technology. As TSV process flows become stabilized, a number of metrology and inspection issues and opportunities have arisen. Many of these challenges are novel to the industry due to the relatively large size of the vias and new processes such as wafer back-grinding and carrier bonding. This paper summarizes the initial trial process monitoring that has been used during via-first TSV process development at IMEC. This process is designed for SiC (system in chip) applications, using Cu-filled vias measuring 5 um wide by 22 or 50 um deep. While there are a variety of metrology and inspection applications for TSV processing, the main topics covered here are via size measurement, post-grind wafer inspection, and carrier wafer bonding inspection.

Process characterization of thin wafer debonding with thermoplastic materials

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on extensive characterization of a thermal debonding approach to answer these challenges.

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down

Among the technological developments pushed by the emergence of 3D-ICs, wafer thinning has become a key element in device processing over the past years. As volume increases, defects in the overall thinning process flow will become a major element of focus in the future. Indeed product wafers arriving at this point of process are of maximum value. Fundamental understanding of the potential defects and their impact on devices is therefore needed to minimize their recurrence.

Extremely Low-Force Debonding of Thinned CMOS Substrate by Laser Release of a Temporary Bonding Material

Over the past few years, temporary bonding has spread together with the development of 3D stacked IC (SIC) technology. Maturity of the various processes has constantly improved. Early processes enabled first demonstration of circuit thinning and thin wafer debonding. Each material generation has brought a step function in the technology maturity, which is now reaching a level allowing first 3D-SIC production. To further answer the refraining elements preventing a more massive technology adoption, novel temporary bonding materials and processes are being developed to reach even lower stress and wafer breakage risks. Hence this contribution deals with the early demonstration of a novel laser release process for ultralow-force debonding.

Demonstration of a novel low cost single material temporary bond solution for high topography substrates based on a mechanical wafer debonding and innovative adhesive removal

Among the technological developments pushed by the emergence of 3D-ICs, wafer thinning has become a key element in device processing over the past years. As technology matures, more emphasis is now being put on the overall cost of ownership, which is still regarded as a refraining element for technology adoption. Therefore novel temporary bond concepts and materials are being explored to further bring down the process complexity and cost.

A Unique Temporary Bond Solution Based on a Polymeric Material Tacky at Room Temperature and Highly Thermally Resistant Application Extension from 3D-SIC to FO-WLP

Among the technological developments pushed by the adoption of Through Silicon Vias and 3D Stacked IC technologies, wafer thinning on a temporary carrier has become a critical element in device processing over the past years. First generation of adhesive materials enabled the integration of the first devices at the expense of capping the thermal budget. Hence new generation materials are being explored to overcome this limitation and further bring the process complexity down.