Anthony M. Balistreri

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Read/write memory having a multiple column select mode

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Read/write memory having an on-chip input data register

Read/write memory having an on-chip input data register, having pointer circuits between a serial data register and input/output buffer circuits

Read/write dual port memory having an on-chip input data register

Graphics display system using tiles of data

Video random access memory having a split register and a multiplexer

Method and apparatus for a design for test, parallel block write operation

Four-bit block write for a wide input/output random access memory in a data processing system