Wilbur C. Vogley

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Time skewing arrangement for operating memory in synchronism with a data processor

Communication bus system between processors and memory modules

Time skewing arrangement for operating random access memory in synchronism with a data processor

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Time skewing arrangement for operating memory devices in synchronism with a data processor

High speed integrated circuit interconnection having proximally located active converter

High-speed clock circuit for semiconductor memory device

Selectable integrated circuit assembly and method of operation

Reduced cost, high speed integrated circuit test arrangement