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Dive into the research topics where Joseph H. Neal is active.

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Featured researches published by Joseph H. Neal.


international solid-state circuits conference | 1986

A 1Mb CMOS DRAM with design-for-test functions

Joseph H. Neal; B. Holland; S. Inoue; Wah Loh; H. McAdams; Ken Poteet

A mask programmable 1Mb CMOS DRAM family has been developed featuring design-for-test functions which allow the memory to reconfigured as an 8b parallel 128Kb organization to reduce test time. With a 1μm twin-well CMOS technology and a contactless trench cell, the chip measures 49mm2.


Archive | 1994

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Wilbur C. Vogley; Anthony M. Balistreri; Karl M. Guttag; Steven D. Krueger; Duy-Loan T. Le; Joseph H. Neal; Kenneth A. Poteet; Joseph P Hartigan; Roger D. Norwood


Archive | 1979

Virtual ground MOS EPROM or ROM matrix

Joseph H. Neal; Paul A. Reed


Archive | 1994

Apparatus and method for a memory unit with a processor integrated therein

Basavaraj I. Pawate; Kenneth A. Poteet; Joseph H. Neal


Archive | 1989

Memory module arranged for data and parity bits

Joseph H. Neal; Kenneth A. Poteet


Archive | 1984

Dynamic memory with improved address counter for serial modes

Bao G. Tran; Joseph H. Neal; Lionel S. White


Archive | 1984

High speed concurrent testing of dynamic read/write memory array

Lionel S. White; Joseph H. Neal; Bao G. Tran


Archive | 1994

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Wilbur C. Vogley; Anthony M. Balistreri; Karl M. Guttag; Steven D. Krueger; Duy-Loan T. Le; Joseph H. Neal; Kenneth A. Poteet; Joseph P Hartigan; Roger D. Norwood


Archive | 1997

Data processing system arranged for operating synchronously with a high speed memory

Wilbur C. Vogley; Anthony M. Balistreri; Karl M. Guttag; Steven D. Krueger; Duy-Loan T. Le; Joseph H. Neal; Kenneth A. Poteet; Joseph P Hartigan; Roger D. Norwood


Archive | 1996

High speed memory arranged for operating synchronously with a microprocessor

Wilbur C. Vogley; Anthony M. Balistreri; Karl M. Guttag; Steven D. Krueger; Duy-Loan T. Le; Joseph H. Neal; Kenneth A. Poteet; Joseph P Hartigan; Roger D. Norwood

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