Roger D. Norwood

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Method and apparatus for inhibiting a predecoder when selecting a redundant row line

High speed, low-power nibble mode circuitry for dynamic memory

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Semiconductor dynamic memory device with multiplexed sense amplifier and write-activated active loads

Glitch suppression circuit

Power-up pulse generator circuit

Clock skew circuit

Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode

Semiconductor dynamic memory device with decoded active loads