Roger D. Norwood | Researchain

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Archive | 1994

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Wilbur C. Vogley; Anthony M. Balistreri; Karl M. Guttag; Steven D. Krueger; Duy-Loan T. Le; Joseph H. Neal; Kenneth A. Poteet; Joseph P Hartigan; Roger D. Norwood

Archive | 1991

Method and apparatus for inhibiting a predecoder when selecting a redundant row line

David V. Kersh; Roger D. Norwood

Archive | 1984

High speed, low-power nibble mode circuitry for dynamic memory

Pravin P. Patel; Roger D. Norwood

Archive | 1994

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Wilbur C. Vogley; Anthony M. Balistreri; Karl M. Guttag; Steven D. Krueger; Duy-Loan T. Le; Joseph H. Neal; Kenneth A. Poteet; Joseph P Hartigan; Roger D. Norwood

Archive | 1984