Benjamin T. Voegeli

Dual-loop direct VCO modulation for spread spectrum clock generation

This paper presents a new spread spectrum clock generator (SSCG) circuit for EMI reduction. The proposed design adopts a standard integer-N phased locked loop (PLL) with two dual-voltage-controlled oscillators (VCOs). A frequency modulation loop is implemented with a digital frequency limit detector to direct the spectrum-spreading profile. An integrator is applied to generate the triangular modulation signal. Comparing with some recent designs [1,2,3,4] in the literature, the spread spectrum clock generator in this paper is simple and area efficient.

A 0.24 μm SiGe BiCMOS technology featuring 6.5V CMOS, f T /f MAX of 15/14 GHz VPNP, and f T /f MAX of 60/125 GHz HBT

For the first time, we report a 0.24 mum SiGe BiCMOS technology that offers full suite of active device including three distinct NPNs, a vertical PNP, CMOS supporting three different operating-voltages, and wide range of passive devices. In particular, this technology provides 6.5 V CMOS capability and VPNP with fT/fMAX of 15/14 GHz and BVCEO of 6.5 V which can be used to complement high breakdown NPN with fT of 30 GHz and BVceo of 6.0 V.

High performance, low complexity vertical PNP BJT integrated in a 0.18/spl mu/m SiGe BiCMOS technology

An isolated vertical PNP BJT with f/sub T/ and f/sub MAX/ of 20GHz available as a modular component in a 0.18/spl mu/m SiGe BiCMOS technology is described. The VPNP device is fabricated using a low complexity integration scheme and is optimized to complement the high breakdown SiGe NPN HBT.