Morin Dehan

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.

Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems

Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC

An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics

Asymmetric doped channel metal oxide semiconductor field effect transistors (MOSFETs) have recently been investigated by several authors in bulk and silicon-on-insulator (SOI) technologies as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage rolloff issues in deep sub-micrometer devices. In this paper, the DC and microwave characteristics of the asymmetric doped channel fully depleted (FD) SOI MOSFET are presented and compared to conventional uniformly doped FD SOI MOSFET.

An improved multiline analysis for monolithic inductors

This paper presents a new efficient multiline model for monolithic inductors. A preliminary model was developed by Huynen, which divided the spiral in sections of coupled transmission lines whose parameters are calculated by a variational principle. This model has been improved for inductors with high trace width-to-gap ratios and it has been demonstrated to be adequate for predicting S-parameters characterizing the inductor over a wide frequency band, even above its self-resonant frequency. This new design tool is shown to be useful for analyzing and optimizing inductor topologies built on both insulating and semiconducting substrates.

Noise modeling and performance in 0.15-μm fully depleted SOI MOSFET

This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.

Comparison of different extraction methods of small-signal parameters for SOI MOSFETs.

For the first time, a comparison is made between different equivalent circuits and different extraction procedures using simulated and measured Silicon-on-Insulator (SOI) MOSFETs. The methods, which will be described, are divided into three categories: the depletion methods, the inversion methods also called cold-FET methods and the saturation methods. Moreover, a novel technique will be presented for the extraction of parasitic capacitances of a MOSFET in deep depletion.

Alternative Architectures of SOI MOSFET for Improving DC and Microwave Characteristics

DC and high frequency characteristics of innovative SOI MOSFETs such as graded channel and dynamic threshold voltage MOS are presented in this paper. These architectures are very promising for high frequency low power low voltage analog applications.

A plug-and-play wideband RF circuit ESD protection methodology: T-diodes

Abstract A novel “plug-and-play” ESD protection methodology for wideband RF applications is demonstrated. This methodology, referred to as T-diodes, utilizes an integrated transformer together with classical ESD protection diodes. The T-diodes act as an artificial transmission line that, when placed as a “plug-and-play” ESD protection component in front of an unprotected wideband LNA, preserves the input matching of that LNA. As a demonstrator, a wideband RF LNA in 0.18xa0μm CMOS is protected above 4.5xa0kV HBM ESD robustness without degrading its bandwidth.