Bon-jae Koo

A 1T/1C Ferrodectric RAM Using A Double-level Metal Process For Highly Scalable Nonvolatile Memory

A double-level metal, one-poly, 1T/lC 64k ferroelectric RAM has been successfully fabricated with 1.2~ conventional CMOS technology. By realizing aluminum bit line, aluminum plate line in the doublelevel metal process without degrading Pt/PZT/Pt ferroelectric capacitor and by adopting lT/lC cell archtecture, lOOns data access time was obtained at Vcc=S.OV which is faster by 40% than the commercialized 2T/2C FRAM with a single-level metal. A proper annealing processes was proved to be the key for the recovery of the ferroelectric capacitor degradation caused by the double-level metal integration process.

A highly reliable 1T/1C ferroelectric memory

A reliable 1T/1C ferroelectric RAM has been successfully fabricated with 1.2 /spl mu/m conventional CMOS technology by adopting IrO/sub 2/ electrode and the Ti-rich PZT thin film. The Ti-rich PZT capacitor shows no degradation of sensing Pr after integration process. After 1/spl times/10/sup 10/ cycling, the loss of remnant polarization was less than 5%. In thermally accelerated (150/spl deg/C) test condition, more than 14 /spl mu/C/cm/sup 2/ for both data 0 and data 1 sensing Pr values are obtained even after 10 years.

Robust Three-Metallization Back End of Line Process for 0.18 µm Embedded Ferroelectric Random Access Memory

We developed ferroelectric random access memory (FRAM)-embedded smartcards in which FRAM replaces electrically erasable PROM (EEPROM) and static random access memory (SRAM) to improve the read/write cycle time and endurance of data memories during operation, in which the main time delay retardation observed in EEPROM embedded smartcards occurs because of slow data update time. EEPROM-embedded smartcards have EEPROM, ROM, and SRAM. To utilize FRAM-embedded smartcards, we should integrate submicron ferroelectric capacitors into embedded logic complementary metal oxide semiconductor (CMOS) without the degradation of the ferroelectric properties. We resolved this process issue from the viewpoint of the back end of line (BEOL) process. As a result, we realized a highly reliable sensing window for FRAM-embedded smartcards that were realized by novel integration schemes such as tungsten and barrier metal (BM) technology, multilevel encapsulating (EBL) layer scheme and optimized intermetallic dielectrics (IMD) technology.

A novel Ir/IrO/sub 2//Pt-PZT-Pt/IrO/sub 2//Ir capacitor for a highly reliable mega-scale FRAM

A novel Ir/IrO/sub 2//Pt-PZT-Pt/IrO/sub 2//Ir capacitor is proposed for a highly reliable mega-scale FRAM. It was observed that charge degradation in retention test depends on the condition of the interface between top electrode and PZT thin film in ferroelectric capacitor. Nonvolatile polarization value of the novel capacitor after the retention acceleration is 4.7 times larger than that of Ir/IrO/sub 2/-PZT-Pt/IrO/sub 2//Ir capacitor. The novel Pt-inserted capacitor shows a great endurance up to 10/sup 11/ fatigue cycles. The 4 Mb FRAM device with Ir/IrO/sub 2//Pt-PZT-Pt/IrO/sub 2//Ir capacitor has a wide sensing window of 90 fC even after baking at 125/spl deg/C for 88 hours.