Hyoung-joon Kim

Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation

first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50 nm contact for sub 50 nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260 muA and thermally stable CVD Ge2Sb2Te5 compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150 nm depth. Our results indicate that the confined cell structure of 50 nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.

Integration of ferroelectric random access memory devices with Ir/IrO2/Pb(ZrxTi1-x)O3/Ir capacitors formed by metalorganic chemical vapor deposition-grown Pb(ZrxTi1-x)O3

Metal organic chemical vapor deposition (MOCVD) of Pb(ZrxTi1-x)O3 (PZT) and its capacitor module process were established for ferroelectric memory device integration. The 130 nm-thick PZT films were deposited on Ir layers at 530°C or 550°C. The remnant polarization of the Ir/IrO2/PZT/Ir capacitors is in the range of 15 to 21 µC/cm2, and their leakage current is 10-5 A/cm2 at 2.5 V without additional annealing. The degradation in their switching endurance is less than 5% after 1010 cycles, indicating that the interfaces formed between the PZT and Ir layers can be optimized to improve their fatigue properties. To evaluate the capacitors on the devices, the conventional backend process was performed after encapsulating the capacitors with AlOx/TiOx layers located on the poly-Si plug. High charge separation and fully functional bit activities were obtained, demonstrating that this MOCVD-PZT process is a reliable integration scheme for high-density ferroelectric memory devices.

Plasma-assisted dry etching of ferroelectric capacitor modules and application to a 32M ferroelectric random access memory devices with submicron feature sizes

In the manufacturing of a 32M ferroelectric random access memory (FRAM) device on the basis of 0.25 design rule (D/R), one of the most difficult processes is to pattern a submicron capacitor module while retaining good ferroelectric properties. In this paper, we report the ferroelectric property of patterned submicron capacitor modules with a stack height of 380 nm, where the 100 nm-thick Pb(Zr, Ti)O3 (PZT) films were prepared by the sol-gel method. After patterning, overall sidewall slope was approximately 70° and cell-to-cell node separation was made to be 80 nm to prevent possible twin-bit failure in the device. Finally, several heat treatment conditions were investigated to retain the ferroelectric property of the patterned capacitor. It was found that rapid thermal processing (RTP) treatment yields better properties than conventional furnace annealing. This result is directly related to the near-surface chemistry of the PZT films, as confirmed by X-ray photoelectron spectroscopy (XPS) analysis. The resultant switching polarization value of the submicron capacitor was approximately 30 µC/cm2 measured at 3 V.

Fabrication of dense contact patterns using halftone phase-shifting mask with off-axis illumination

We have investited the performance of the halftone phase-shifting mask (HT PSM) with various illuminations for contact patterns of different pitches in DUV photo lithography . It was found that illumination could be optimized as a function of the pitch. Highly coherent illumination was the best for isolated contact patterns but it was the worst for extremely dense contact patterns due to optical proximity effect and interference which occurred between the primary peaks and the secondary peaks of neighboring contact holes. For extremely dense contact patterns, off-axis illumination (OAI) was found to be the most appropriate compared to conventional illuminations because extremely dense contact patterns show the optical proximity effects which was observed similarly for equal line and space patterns. We found that HT PSM combined with OAI can be used for fabricating the extremely dense contact patterns of high density devices such as 256M and 1 G bit DRAM.

DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug

As DRAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned contact (SAC) is the most critical problem for integration of capacitor-on-bitline (COB) DRAM devices because it is one of the deepest contacts with high aspect ratio; and it reaches the cell transistor junction. However, few reports have addressed this issue, while others have been reported elsewhere (Song et al., 2000; Jeong et al., 2000; Won et al., 2000; Kim et al., 2000). In this paper, a novel process of bitline spacerless storage node SAC and Ru-Ta/sub 2/O/sub 5/-Ru (RIR) capacitor with TiN contact plug is studied for the integration of 0.1 /spl mu/m design-rule based DRAMs. It was found that the spacerless SAC process made downscaling to the 0.1 /spl mu/m design-rule possible and also that it has better electrical properties than the conventional SAC.

NA optimization of 360-nm and 300-nm pitch devices

KrF extendibility to 180 nm and 150 nm L/S patterns and optimized NA were investigated by simulation. Mask CD error and exposure dose error are very important factor in photo process of device manufacture. We took 2 level of expected mask quality and dose control. The mask CD error of plus or minus 15 nm and dose error of plus or minus 4% are very tight but possible level in near future, and plus or minus 10 nm and 3% as extremely tight level but expected to be achieved in sometime. 0.6 NA and quadrupole illumination (pole offset 0.75, diameter 0.1) shows 0.8 micrometer depth of focus (DOF) with mask CD error of plus or minus 15 nm and dose error of plus or minus 4% for 180 nm patterns and bigger in our simulation. This shows that the 0.6 NA KrF exposure tool could be applied to 180 nm devices with acceptable mask and dose errors, but there are still problems of illumination uniformity and throughput caused by extreme off axis condition. Including 150 nm pattern, only 0.7 NA shows 0.6 micrometer DOF with mask CD error of plus or minus 10 nm and dose error of plus or minus 3% which is extremely tight condition.

Defect inspection and printability of deep-UV halftone phase-shifting mask

As feature size goes down to a quarter micron, halftone phase- shifting mask (HT PSM) has been studied to extend photo lithography capabilities especially in contact hole patterns. However, defect problem of HT PSM is more serous than that of conventional chrome mask because of added reticle fabrication process steps in which unexpected defects can be generated. In this paper, test HT PSMs which have different transmittance at 488 nm and same background contact patterns with programmed defects having various types are investigated for 250 nm contact hole patterns. The programmed defect are used for the sensitivity evaluation of reticle inspection systems, i.e. detectability and exposed by 4X reduction DUV exposure tool to determine printability and water defect detectability. Direct reticle inspection results show that the detectability depends on transmittance at the inspection wavelength 488 nm. The printability from the wafer exposure results is proportional to defect area strongly. Indirect reticle inspection results using an imaged wafer and wafer inspection tool of SEMSpec show that direct reticle inspection is better than indirect inspection.