C. Y. Lu

A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory

Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

Sub-30nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory window is also larger than the bulk planar devices due to the tri-gate structure that enhances the electric field during programming/erasing. However, a fair percentage of devices contain grain boundaries with poorer S.S. and gm. Interestingly, this only affects the DC characteristics but does not impact the memory window. Furthermore, grain boundaries do not increase the random telegraph noise. The most serious drawback of grain boundaries is the impact on self-boosting window caused by junction leakage. A sub-30 nm TFT BE-SONOS NAND device with MLC capability and good retention is demonstrated

A Highly Reliable Self-Aligned Graded Oxide WO x Resistance Memory: Conduction Mechanisms and Reliability

WOx formed by plasmas oxidation shows promising multi-bit/cell resistance memory characteristics (ChiaHua Ho et al., 2007). The simple memory is completely self-aligned, requiring no additional masks and has a small 6F2 cell size. In this work we introduce a graded oxide device that is highly reliable (250degC baking for > 2,000 hrs). The conduction mechanism and factors affecting the memory reliability are examined extensively.

A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

For the first time, a successful TFT NAND-type flash memory is demonstrated using a low thermal budget process suitable for stacking the memories. A TFT-SONOS device using bandgap engineered SONOS (BE-SONOS) (Lue, et al. 2005) with fully-depleted (FD) poly silicon (50 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.18/0.09 mum) with good DC performance are achieved, owing to the good control capability of the tri-gate FD structure. Successful NAND array functions are demonstrated, with more than 1 muA read current for a 16-string NAND array and good program disturb immunity. This new device also shows good endurance and data retention, and negligible read disturb. These results are very encouraging for future 3D flash memory

Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)

The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary to suppress the parasitic leakage path and avoid the abnormal subthreshold current behavior. Second, the edge fringing field effect significantly changes the P/E speed and degrades the incremental-step-pulse programming (ISPP) slope from ideal value (=1). The complexity of the edge fringing field cannot be modeled by simple 1D tunneling, and by using 3D simulation we found that the edge fringing field greatly degrades the tunnel oxide electric field especially after electrons are programmed into the channel. Moreover, because of edge fringing field effect more charge injection is required to obtain the same memory window when the device is scaled. We propose an analytical ISPP model. A field enhancement factor (FE) is introduced, and the FE gradually decreases with electron injection while Vt gets higher. Through this model the ISPP programming of various STI structures can be well understood. Finally, we find that the self-boosting program disturb window is proportional to the ISPP slope.

A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface

For Solid-State Drive (SSD) applications cycling endurance of NAND flash is a critical challenge. In this work the endurance reliability of BE-SONOS NAND is thoroughly examined. Using dual CV/IV tests the impact of interface state (Dit) generation/annealing and real charge trapping (Q) on the endurance degradation has been clearly identified. For BE-SONOS with pure thermal oxide O1, the endurance degradation mainly comes from Dit generation at Si/O1 interface, while charge trapping in the thin ONO barrier is negligible even after 100K cycles of stressing. Meanwhile, the high-temperature VT loss mainly comes from interface state annealing, while the real charge loss due to electron de-trapping is much smaller. This indicates that our nitride-trapping device has “deep” traps that well retain charges even after the tunnel barrier is damaged. Based on this understanding, we have introduced nitrided O1 to strengthen the Si/O1 interface, and both the endurance and retention are greatly improved. We demonstrate high-endurance BE-SONOS NAND devices of P/E ≫ 5K for MLC and P/E ≫ 100K for SLC operations with excellent retention, promising for solid-state drive (SSD) applications.

A comprehensive comparison between double patterning and double patterning with spacer on sub-50nm product implementation

In this study, DP (Double Patterning) and DPS (Double Patterning with Spacer) were comprehensively compared through word line layout of 50nm node product, and special focus was put on the assessments of layout discontinuity zones through experimental validation. In conventional flash manufacturing, the lithographic proximity effect and etch loading effect around the array-gap zones have been inherent characteristics to be addressed. For DP process, apart from the overlay error induced pattern displacement and CD non-uniformity, the cross-coupling effects between adjacent features around the array-gap zones by two photo and two etch steps have further complicated the process optimization, therefore careful exploration was carried out to indicate the challenges on process optimization. The DPS can maintain good resultant CD uniformity of dense array through precisely programmed exposure CD and spacer thickness, it may also keep away from the proximity around array-gap zones. But, the second exposure is necessary for trimming the unwanted patterns and delineating the peripheral patterns. In purpose of trimming the unwanted patterns at array-gap zone in the 2nd exposure, the overlay registration will account for the CD control of boundary lines as well as the defectivity around this area.

Current Status and Future Challenges of Resistive Switching Memories

Resistive switching memories (ReRAM), including transition metal oxide memory (TMO-RAM) and conducting bridge memory (CB-RAM), are some of the most promising new technologies that may scale beyond the charge-storage flash memories. Understanding the fundamental operation mechanism is one important challenge to control the key parameters and to choose the ReRAM material. The knowledge on ReRAM reliability is also insufficient to meet the future challenges. This paper will review the recent major approach of WOX ReRAM and Cu-based CB-RAM. Introduction Conventional charge-storage non-volatile memories are approaching their scaling limit [1]. A number of new non-volatile memories have been proposed [2-5] and among them the resistive switching memory is considered one of the most promising candidates [4-5]. To enable this new technology, researchers and engineers are working on four major topics: write power, scaling possibility, ReRAM materials, and cross point array architecture. The write power of ReRAM is lower than several other emerging memories such as PCM and MRAM [6-8]. However, the high forming voltage/current is still a concern, and even the regular write current affects the bandwidth. Although devices smaller than 10nm have been reported [7-8] recently, but array uniformity and reliability are still not proven. And finally, a proliferation of ReRAM materials has yet to converge to a few exhibiting all desired properties. ReRAM Materials Fig. 1 shows the ReRAM feature size evolution compared with charge-storage memory [7-19]. Already ReRAM has passed the scaling limit of charge-storage memories. Fig. 2 shows the relationship between switching current and speed [7-19]. The observation that only a few points are in the low-current/high-speed region indicates that there may exist a tradeoff between operating current and switching speed. The fact that most of the transition metal oxides can be switched not only in bipolar but also in unipolar modes actually triggers a critical issue on how to choose the best material and the best operation mode. Thus fundamental material studies including the switching mechanism, the conducting mechanism, and the material characteristics are the most important topics in ReRAM research. There seems consensus now that the bipolar switching behavior of TMO-RAM and CB-RAM is dominated by the movement of anions (Valency change effect) and cations (Electrochemical effect) (Fig. 3a and 3b) [9,18]. For unipolar opeation, it is believed that the switching mechanism is based on thermochemical effect (Fig. 3c) [20]. However, the detailed physical models still need further improvements and the knowledge for fine tuning the physical parameters to improve the device performances including speed, current, resistance window, data retention, and cycling endurance is still under development. Field Enhancement Structure for WOX ReRAM Since the forming process is an important issue and needs to be solved, a self-aligned field-enhancement device structure is proposed and its 2D simulation for 20 and 100 nm cells are shown in Fig. 4. By oxidizing the TiN liner into an insulating TiNOX the WOX is forced to protrude above the remaining TiN. Fig. 5a shows significantly higher electric field at the center of the WOX when the size of the W plug scales. Fig. 5b shows that the voltage required for the initial forming process falls rapidly when the cell size scales. Therefore, at 60nm or below, the initial forming process is practically eliminated. The 60nm WOX device not only shows forming-free property, but also good electrical performance. Fig. 6a shows the cycling endurance of the 60nm devices is > 10 times, and a 10X resistance window is well maintained by program-verify algorithms. Excellent thermal stability is Fig.1. Evolution for ReRAM and charge-storage memory. ReRAM shows promising scalability beyond 1X nm technology node. Fig.2. Switching current versus switching time for both TMO-RAM and

A novel cross point one-resistor (0T1R) conductive bridge random access memory (CBRAM) with ultra low set/reset operation current

Using the dual Vth characteristics of a multi-layer SiO2/SiO2/Cu-GST conducting bridge (CB) structure we can construct a one-resistor cell without an access device (0T1R). Like 1T Flash memory the Vth is used to store the logic state thus leaving all devices always at high resistance state and a separate isolation device is not needed. The Vth of the cell is determined by the presence of CB in the SiO2 layer only. The CB in the SiO2 is present only temporarily during reading, and is spontaneously dissolved afterward. This spontaneous rupture of the filament in the SiO2 layer greatly reduces the switching current as well as reducing the read disturb. The mechanism for the spontaneous rupture phenomenon is investigated.

A Novel Ni/WOx/W ReRAM with Excellent Retention and Low Switching Current

W.C. Chien, Y.C. Chen, F.M. Lee, Y.Y. Lin, E.K. Lai, Y.D. Yao, J. Gong, S.F. Horng, C.W. Yeh, S.C. Tsai, C.H. Lee, Y.K. Huang, C.F. Chen, H.F. Kao, Y.H. Shih, K.Y. Hsieh, and Chih-Yuan Lu Emerging Central Lab., Technology Development Center, Macronix International Co., Ltd., Hsinchu, Taiwan, R.O.C. Department of Physics and Institute of Applied Science and Engineering, Fu Jen University, Taipei, Taiwan, R.O.C. Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.