Carl Chen

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

Development of 25-

The development of ultrafine-pitch microbumps and the thermal compression bonding (TCB) process for advanced 3-D stacking technology are discussed in this paper. Microbumps, consisting of Cu pillars and thin Sn caps with a pitch of 25 μm, are fabricated on an Si chip by the electroplating method. Total thickness of the Cu pillar and the Sn cap is 10 μm. Electroless nickel and immersion gold pads with a total thickness of 4 μm are fabricated on an Si carrier. TCB of the Si chip and the Si carrier is conducted on an FC150 flip-chip bonder, and a good joining with higher than 10-MPa die shear strength is achieved. After bonding, the bond line thickness between the Si chip and the Si carrier is filled with the selected capillary underfill material. Void-free underfilling is achieved with underfill materials which have a fine filler size. Ninety percent of the bonded samples can pass the thermal cycling test (-40/+125°C) with 1000 cycles and the highly accelerated temperature/humidity stress test (130°C , 85% RH) for 96 h.

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Flux used in 25um ultra fine pitch flip chip attachment process has been found to play an important role in the bump joint and performance. It is commonly used in cleaning the surfaces of solder balls and the surfaces to be soldered to ensure a good wetting of the solder bumps on the substrate pads. Here we use Cu pillar bump with solder cap and substrate pad surface finish is plating tin, and furthermore the standard reflow process was used to perform the evaluation. Due to higher bonding temperature requirement, a Pbfree compatible no clean flux is needed. This kind of flux is formulated to work well with small bump diameter and pitch which have low residual after reflow profile and low weight loss during the whole process. Of course they are achieving compatibility with the underfill. For this new generation flip chip products, how to select a suitable flux is the most challenge. This paper gives a detailed description of the challenges encountered during assembly, such as the flux selection process, flux height study. The characteristics of flux can be determined by using TGA, wet-ability test, and thermal resistance. For ultra fine pitch flip chip application, no clean and low residue flux is the basic demand. Besides, jetting type flux will be the best choice because the flux height is hard to control and the flux amount might not be enough to provide the solder joint ability. Finally, we conclude that the most rigid bonding method, and parameter for fine pitch Cu pillar bump flip chip package.

-Pitch Microbumps for 3-D Chip Stacking

The wafer level hermetic packaging is a method of sealing micro-devices containing movable parts with a capping wafer in vacuum. The capping wafer is etched to form a cavity which will cover over the MEMS devices and the process is carried out at the wafer level before the device wafer is diced. Glass frit bonding is described as the most leak proof and robust sealing mechanism of all available methods. In this approach, the glass frit is stencil printed on the wafer and the wafer is thermo compression bonded to the subject device wafer under tightly controlled pressure in vacuum with 1000mBar of force at 440°C temperature for 10 minutes. This bath processing method gives cost advantages due to the process time reduction and hermetic seal over the wafer level packaging (WLP). The widths of seal ring were singulated to 4 different dimensions (200, 150, 100 and 50um) for leak rate test. The performance of this 0.2∗0.2cm2 package shows lower leak rate even at 50um width seal ring. These devices also pass the level 3 reliability test and keep high hermetic performance (lower than 7∗10–9 atm∗cc/s).

Flux study for ultra fine pitch flip chip packages

In recently years, the continued demand for electronic systems and subsystems with more functionality, higher electrical performance, smaller size and lower cost, the conventional packaging and interconnect technologies already can not be met for its requirement, so system-in-package (SiP) modules have been growing rapidly. As a packaging technology platform, SiP allows a high degree of flexibility, high-density, high-speed, high performance, and multi-function in the package architecture. But, the form factor and electrical performance of system-in-package(SiP) is still continue to be driven by the next generation portable electronics. Recently, many company and research institute addressed embedded active and passive substrate technology development is the one of approach for the requirement. However, there are many electrical and mechanical reliability issues in embedded substrate. A mismatch of coefficient of thermal expansion (CTE) among substrate materials and structure can lead to large warpage, stress, delamination, crack or copper via break in the substrate. Thermal deformations and thermal stresses may occur due to mismatches of the coefficient of thermal expansion, Tg (Temperature of Glass transition), Youngs modulus among the substrate materials during assembly process as well as service conditions, which lead to serious quality problems and failure of the products. It were conducted to be analyzed the stress and warpage during thermal cycle loading by Finite Element Method (FEM). At the beginning, a FE model was created; FE calculations were carried out in order to study the different substrate core and prepreg material effect on warpage and stress during thermo-mechanical history. And then, different substrate thickness, embedded component quantity also be conducted to analyze the warpage and stress during thermal history. For interface stress between via and prepreg material of embedded capacitor or die substrate, the CTE of core material which is closed to Cu via CTE (16.3 ppm/°C) generates lower via shear stress. For capacitor component stress, the CTE of core material which is closed to passive (12.3ppm/°C) & via land (16.3ppm/°C) generates lower component shear stress. For die stress, the CTE of core material which is closed to die (2.6ppm/°C) generates lower component shear stress.

High hermetic performance of glass frit for MEMS package

The submodeling technique is a powerful analysis tool. The method promotes more accurate analysis and also helps enhance productivity. It has been shown that by using displacement-force cut boundary condition method, it can be made even more versatile. The local stress phenomena of the solder microbump have been solved with this approach to demonstrate the concept. From the simulation model, it is known that the ENIG pad thickness has an effect on the aluminium pad stress in the silicon chip. This is important as the shear stress will damage the pad and circuitry on the chip. Previously this is not reported in other literatures as there is no strain gage available that can measure such a small dimension.

The warpage and stress simulation study of embedded organic substrate

In recent years, electronic product have been demanded more functionalities, miniaturization, higher performance, reliability and low cost. Therefore, IC chip is required to deliver more signal I/O and better electrical characteristics under the same package footprint. None-Lead Bump Array (NBA) Chip Scale Structure is then developed to meet those requirements offering better electrical performance, more I/O accommodation and high transmission speed. To evaluate NBA package capability, the solder joint life, package warpage, die corner stress and thermal performance are characterized. Firstly, investigations on the warpage, die corner stress and thermal performance of NBA-QFN structure are performed by the use of Finite Element Method (FEM). Secondly, experiments are conducted for the solder joint reliability performance with different solder coverage and standoff height In the conclusion of this study, NBA-QFN would have no warpage risk, lower die corner stress and better thermal performance than TFBGA from simulation result. Beside that, the simulation result shows good agreement with experimental data. From the drop test study, with solder coverage less than 50% and standoff height lower than 40um would perform better solder joint life than others.

Sub-modeling technique for thermo-mechanical simulation of solder microbumps assembly in 3D chip stacking

Since 3D-IC becomes popular nowadays, solder micro-bumps plays an important role to develop TSV technology. This study verifies solder micro-bump efficiency via cracking as index. The micro-bump cracking is observed at the interface of intermetallic compound (IMC) layer after Si chip and Si carrier bonding. It was found that P-rich Ni layer will perform weaker and brittle solder joint by means of EDS. Figure 1 shows the cross section schematic drawing as 3D chip stacking for a Si chip and a Si carrier. The solder micro-bumps and under bump metallurgy (UBM) pads are fabricated on the Si chip and the top side of Si carrier respectively. The TSVs in Si carrier functions as interconnects. After flip chip assembled Si chip and Si carrier, the whole assembly is joint onto a bismaleimide triazine (BT) substrate with redistribution layer and solder joints through by bottom of Si carrier. In this study, the Si carrier was patterned with the diameter and depth by 50um and 120um respectively at room temperature with BOSCH process. The smoother scallop was achieved below 150nm. Excellent passivation step coverage for 39% ≃ 50% from via top to bottom side was also obtained. TSV formation processed by electroplating Cu and X-ray result shows void free in TSV. After TSV formation, the electrical nickel and immersion gold (ENIG) was used for the UBM. The total thickness of 50μm Ni/Cu and Sn/Ag solder micro bumps were fabricated by electroplating on top of Si chip.

Package characterization on advanced NBA-QFN structure

In order to uniformly expose Cu via, TSV wafer thinning becomes much critical contrary to conventional process. The complete wafer thinning process is expected composed of not only grinding, but also handling. This study develops advance wafer thinning process from temporary carrier bonding to carrier de-bonding that also includes grinding and backside processes. In this case, the bonded wafer thinning target is 100um for backside process. Void-free carrier bonding and bump after backside processes could be addressed. The carrier de-bonding process performs no wafer crack and residue. Moreover, whole wafer thinning process never suffers from Cu scratching. In this study, Under Bump Metallization (UBM) and bump were laid on the backside of Through Silicon Via (TSV) wafer. The wafers composed of various surface structures were carried out to bond glass carrier. The structure difference above came from various designs on UBM and bump. These designs may be backside UBM only, Redistribution Layer (RDL) + UBM, and even bumps on UBM. All the wafers were prepared through passivation patterning, sputtering, solder printing, plating and reflow. Among these processes, the wafer preparation also requires necessary passivation curing, sputtering for Cu seed deposition, and electroplating to form solder bump.

Three dimensional interconnects with through silicon vias and electroplating solder microbumps

The trend of semiconductor advance packaging development is toward fine pitch and high I/O density. Wafer level package is good way to resolve fine pitch and high I/O density IC productions, especially package tape of Wafer Level Chip Scale Package (WLCSP). In traditional bumping process, such as printing [1], electric-plating [2] and ball mount [3–5], it is done by producing bumps on wafers. The paste printing technologies are very versatile with respect to the alloy composition that can be use, but is limited to pitches around 200um for 100um tall bumps. The electric-plating technique is somewhat limited for use in smaller facilities due to the high capital and operation costs. In addition, ternary alloys, like SnAgCu are difficult to plate with consistent results. There is also a practical upper limit to the size of the bump that can be produced, and most applications rare for fine pitch bumping. Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer which with high throughput and consistent bump results. Ball mounts process without using electric-plating electrolyte decrease cost and chemical pollution. This technique is applicable for many applications but there are several issues are associated with this technology that limits its widespread use in high volume and high yield applications. These limitations include of there is a practical lower limit to the size of sphere that can be dropped, the stencil between the performed solder spheres and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and the yields are statistically low. To get high I/O density IC request, the trend of WLCSP I/O pad distributed design is toward to reduce I/O pitch and increase I/O density, and therefore impact solder ball size application of ball mount process, WLCSP Micro-ball mount technology is requested. There are several issues are associated with this technology that certain ball dropping position and escape issue. The most important factors associated with performance of Micro-ball mount technology are accurate dropping parameter, stencil quality and reflow condition. In this paper, we successfully produced WLCSP Micro-ball which diameter lower than 100um with bump pitch 130um onto 300mm wafers. Yield more than 99.99% without missing bump and bridge bump were realized for placing 70um spheres onto wafers with ∼2KK I/Os.