Charles Edward Drake

A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection

Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving board space and reducing power. Multichip-module (MCM) packaging further optimizes the electrical characteristics of the processor-cache connection. An in-line level-2 1 MB cache chip that has DRAM density contains high-speed SRAM and MCM technology.

A 50 ns 16 Mb DRAM with a 10 ns data rate

A 16-Mb DRAM chip fabricated in a 0.5- mu m CMOS process using silicided polysilicon, double metal, and trench storage is described. It incorporates an architecture that supports either 11/11 or 12/10 RAS/CAS (row-address strobe/column-address-strobe) addressing. It is segmented to utilize bit redundancy of 2 lines/137-b lines/half quadrant, and separate word-redundant array of 24 lines/quadrant, providing any-for-any-word-line replacement within a quadrant. It has single-error-correct/double-error-detect (SEC/DED) error checking and correcting (ECC) Hamming odd-weight code/quadrant and either 5-V or 3-V operation. The design provides a RAS access of 50 ns with 16-ns fast-page access, 18-ns static column or toggle of 10 ns at 2.9 V and 85 degrees C. DRAM features are summarized.<<ETX>>