Chien-Chou Chen

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers

The effects of etch rate on TSV sidewall variation in 8” (200mm) and 12” (300mm) wafers are investigated in this study. Emphasis is placed on the determination of sidewall scallop with different etch rates ranging from 1.7μm/min to 18μm/min and various TSV diameters (1μm, 10μm, 20μm, 30μm, and 50μm) by design of experiments (DoE). The BHE in/out (2666Pa/2666Pa) are the same for all the cases. Also, characterizations of the sidewall scallop are performed by cross sections and scanning electron microscopy (SEM). Furthermore, with a same etch recipe, mask, and 9 (5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 40μm, 55μm, and 65μm) TSV diameters, the etch results such as etch rate, TSV depth, and sidewall scallop of 200 and 300mm wafers are provided and compared, Finally, a set of useful process guidelines and recipes for optimal TSV etching is presented.

Design, fabrication, and calibration of stress sensors embedded in a TSV interposer in a 300mm wafer

In this study, the design, fabrication, and calibration of the piezoresistive stress sensors [1-18] embedded in a TSV (through silicon via) interposer in a 300mm wafer are investigated. The results presented herein should be useful for the development of 3D integration such as measuring the strength of the TSV device and interposer wafers, during and after all the processes such as wafer thinning, SiO2 deposition, metallization, and electroplating.

Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer

TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≤50 μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.

Key enabling technologies of 300mm 3DIC process integration

Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.

Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications

Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3D IC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.

An innovative bumpless stacking with through silicon via for 3D Wafer-on-Wafer (WOW) integration

An adequate sequential etching though dielectrics, silicon and permanent adhesive material was successfully developed for the damascene interconnects in the face-to-back bumpless TSV Wafer on Wafer (WOW) processes. The induced bowing taken place at the etching of permanent adhesive was optimized and no void Cu metallization was achieved. According to those TSV technology, the upper and lower stacked wafers was electrically connected without bump electrodes. The improved process such as chemical mechanical planarization (CMP) of Cu re-distribution layer (RDL) is also developed successfully to provide uniform and straight line resistance distribution and reduce the loading of TSV over-etching to avoid the interconnect open issue.

Low-cost 3DIC process technologies for wide-I/O memory cube

Low-cost 3DIC process approaches are investigated in terms of 3D stacking method and TSV process integration scheme. The permanent and bumpless wafer-to-wafer (PBWW) bonding technology can be applied to the DRAM wafers in the wide-I/O memory cube application. Backside TSV process with its electrical characteristics is also studied. The combination of these two process technologies can further lower the overall process cost and speed up the mass production.

Study of TSV filling performance with wide-range pattern densities by using a novel plating chamber with surface paddle agitation

TSV (through silicon via) metallization is one key process in 3DIC integration. Due to high aspect ratio and filling volume, TSV copper plating is the most time-consuming module in the whole process flow. To increase the throughput of electroplating, tool configurations and plating chemistry should be optimized. In this work, an electroplating chamber with a novel paddle design is used in this experiment to study the effects of paddle agitation on plating performance. The influence of this paddle design on different TSV pattern density and geometric scheme are also investigated.