Tzu-n Ku

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated.

Novel Defects-Trapping

The dependence of resistive switching of Ta/TaOX/HfOX device governed by general filamentary or novel defects-trapping mechanism on the operation current is demonstrated in this letter. The device with stable resistive switching, high nonlinearity, and robust self-compliance ~ 1 μA is demonstrated, which can be integrated in the vertical RRAM structure. Based on constant current density switching ( ~ 103 A/cm2) governed by defects-trapping transport, where the low and high resistance states attributed to the resistance of Ta/TaOX layer and device initial state, the switching current reduction by scaling down the cell size is proposed in transition metal oxide RRAM.

{\rm TaO}_{\rm X}/{\rm HfO}_{\rm X}

Many big-data (BD) processors reduce power consumption by employing ternary content-addressable-memory (TCAM) [1-2] with pre-stored signature patterns as filters to reduce the amount of data sent for processing in the following stage (i.e., wireless transmission). To further reduce standby power, BD-processors commonly use nonvolatile memory (NVM) to back up the signature patterns of SRAM-based TCAM (sTCAM) [3] during power interruptions or frequent-off operations. However, this 2-macro (sTCAM + NVM) scheme suffers long delays and requires considerable energy for wake-up operations, due to the word-by-word serial transfer of data between NVM and TCAM macros. Most of the signature patterns are seldom updated (written); therefore, single-macro nonvolatile TCAM (nvTCAM) can be used for BD-processors to reduce area and facilitate fast/low-power wake-up operations, compared to the 2-macro approach. Previous nvTCAMs were designed using diode-connected 4T2R with STT-MTJ (D4T2R) [4], 2T2R with PCM [5], and 4T2R with ReRAM [2]; however, they suffer the following issues: (1) large cell area (A) and high write energy (Ew) due to the use of two NVM (2R) devices; (2) limited word-length (WDL, /k-bits) caused by small current-ratio (I-ratio= IML-MIS/(K×IML)) between match-line (ML) mismatch current (IML-MIS) and ML leakage current of k matched cells (k × IML-MIS); (3) Long search delays (TSD) and excessive search energy (Es) due to large ML parasitic load (CML) and small I-ratio. ReRAM is promising for nvTCAM due to its low Ew, high resistance-ratio (R-ratio), and multiple-level cell (MLC) capability. To overcome issue (1) to (3), this study develops an MLC-based 3T1R nvTCAM with bi-directional voltage-divider control (BVDC). A 2×64×64b 3T1R nvTCAM macro is fabricated using back-end-of-line (BEOL) ReRAM [6] and a 90nm CMOS process, with 2.27× cell size reduction as compared with sTCAM using the same technology and the TSD (=0.96ns) for WDL=64b.

RRAM With Reliable Self-Compliance, High Nonlinearity, and Ultra-Low Current

This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128×32b RCSD nvTCAM macro was fabricated using HfO ReRAM and an 180nm CMOS. This paper presents the first ReRAM-based nvTCAM featuring the shortest (1.2ns) search delay (TSD) among nvTCAMs with WDL≥32b.

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time

This study proposes a 7T1R nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single NVM device, 2) suppress DC-short current during restore operations through the use of a pulsed-overwrite (POW) scheme, and 3) achieves high restore yield by using a differentially supplied initialization (DSI) scheme. This initialization-and-overwrite (IOW) 7T1R nvSRAM improves breakeven-time (BET) by 6+x, compared to previous nvSRAMs. We fabricated a 16Kb IOW-7T1R nvSRAM using HfOx RRAM and a 90nm process. This represents the first ever silicon verified single-NVM nvSRAM macro. Measurements obtained in test-mode confirm that the proposed nvSRAM reduces store energy by 2x and restore energy by 94x, compared to 2R-based nvSRAMs.

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications

The effects of etch rate on TSV sidewall variation in 8” (200mm) and 12” (300mm) wafers are investigated in this study. Emphasis is placed on the determination of sidewall scallop with different etch rates ranging from 1.7μm/min to 18μm/min and various TSV diameters (1μm, 10μm, 20μm, 30μm, and 50μm) by design of experiments (DoE). The BHE in/out (2666Pa/2666Pa) are the same for all the cases. Also, characterizations of the sidewall scallop are performed by cross sections and scanning electron microscopy (SEM). Furthermore, with a same etch recipe, mask, and 9 (5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 40μm, 55μm, and 65μm) TSV diameters, the etch results such as etch rate, TSV depth, and sidewall scallop of 200 and 300mm wafers are provided and compared, Finally, a set of useful process guidelines and recipes for optimal TSV etching is presented.

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

In this study, the optimization of Cu CMP performance (dishing) for removing thick Cu plating overburden due to Cu plating for deep TSVs in a 300mm wafer is investigated. Also, backside isolation oxide CMP for TSV Cu exposure is discussed. In order to obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu polishing process. The bulk of Cu is removed with the slurry of high Cu removal rate at the first step and the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly-optimized Cu plating overburden for TSVs and RDLs. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a bigger via size still keep in a plateau-like shape after CMP.

Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers

Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energy-efficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memrisitive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.