Yu-Chen Hsin

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers

The effects of etch rate on TSV sidewall variation in 8” (200mm) and 12” (300mm) wafers are investigated in this study. Emphasis is placed on the determination of sidewall scallop with different etch rates ranging from 1.7μm/min to 18μm/min and various TSV diameters (1μm, 10μm, 20μm, 30μm, and 50μm) by design of experiments (DoE). The BHE in/out (2666Pa/2666Pa) are the same for all the cases. Also, characterizations of the sidewall scallop are performed by cross sections and scanning electron microscopy (SEM). Furthermore, with a same etch recipe, mask, and 9 (5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 40μm, 55μm, and 65μm) TSV diameters, the etch results such as etch rate, TSV depth, and sidewall scallop of 200 and 300mm wafers are provided and compared, Finally, a set of useful process guidelines and recipes for optimal TSV etching is presented.

Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure

In this study, the optimization of Cu CMP performance (dishing) for removing thick Cu plating overburden due to Cu plating for deep TSVs in a 300mm wafer is investigated. Also, backside isolation oxide CMP for TSV Cu exposure is discussed. In order to obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu polishing process. The bulk of Cu is removed with the slurry of high Cu removal rate at the first step and the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly-optimized Cu plating overburden for TSVs and RDLs. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a bigger via size still keep in a plateau-like shape after CMP.

Process integration of 3D Si interposer with double-sided active chip attachments

A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.

Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer

TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≤50 μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.

Key enabling technologies of 300mm 3DIC process integration

Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.

Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications

Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3D IC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.

Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

Hardware implementation of physically unclonable function (puf) in perpendicular STT MRAM

The pSTT MRAM array with stepped structure MTJ is fully integrated with standard 0.18 µm CMOS process. Using a low power etch process greatly improves the uniformity of MR and RP. The bit pattern is randomized with a voltage method and a cost-effective field method; the latter can be incorporated into wafer processing. We showed the bit pattern is unpredictable under the same sub-critical stimulation, thus, practically unclonable. The Hamming Weight and inter-chip Hamming Distance are both ∼50%, an evidence of sufficient uniqueness. A single embedded STT-MRAM PUF can cover many needs of security electronics.

Backside-TSV process development and integration for 2∼3um small size TSV

In this paper, we show the process and integration results of small TSVs integrated by 300mm 3DIC BTSV process. The TSV size is from 2um to 3um (in diameter) with aspect ratio of 10. The achievements of this work are: 1) successful demonstration of 20um thin wafer process by ITRIs 300mm wafer thinning process; 2) 2~3um TSV patterning and etching performed by backside TSV process; 3) Combination of the contact aligner and scanner alignment mark systems to explore the backside process capability of scanner for the first time; 4) Completion of the liner deposition, bottom oxide break and TSV filling of 3um TSV to realize the small size TSV integration; 5) Verification of 3um-diameter and 30um-depth BTSV by daisy chain electrical measurement with the yield of 75% in 1360ea TSV. The result shows the integration feasibility of BTSV with small size TSV for high area penalty concern products.