Po-Chih Chang

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

Process integration of 3D Si interposer with double-sided active chip attachments

A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.

Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer

TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≤50 μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.

Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications

Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3D IC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.

Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration

Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.

An innovative bumpless stacking with through silicon via for 3D Wafer-on-Wafer (WOW) integration

An adequate sequential etching though dielectrics, silicon and permanent adhesive material was successfully developed for the damascene interconnects in the face-to-back bumpless TSV Wafer on Wafer (WOW) processes. The induced bowing taken place at the etching of permanent adhesive was optimized and no void Cu metallization was achieved. According to those TSV technology, the upper and lower stacked wafers was electrically connected without bump electrodes. The improved process such as chemical mechanical planarization (CMP) of Cu re-distribution layer (RDL) is also developed successfully to provide uniform and straight line resistance distribution and reduce the loading of TSV over-etching to avoid the interconnect open issue.

Backside-TSV process development and integration for 2∼3um small size TSV

In this paper, we show the process and integration results of small TSVs integrated by 300mm 3DIC BTSV process. The TSV size is from 2um to 3um (in diameter) with aspect ratio of 10. The achievements of this work are: 1) successful demonstration of 20um thin wafer process by ITRIs 300mm wafer thinning process; 2) 2~3um TSV patterning and etching performed by backside TSV process; 3) Combination of the contact aligner and scanner alignment mark systems to explore the backside process capability of scanner for the first time; 4) Completion of the liner deposition, bottom oxide break and TSV filling of 3um TSV to realize the small size TSV integration; 5) Verification of 3um-diameter and 30um-depth BTSV by daisy chain electrical measurement with the yield of 75% in 1360ea TSV. The result shows the integration feasibility of BTSV with small size TSV for high area penalty concern products.

Low-cost 3DIC process technologies for wide-I/O memory cube

Low-cost 3DIC process approaches are investigated in terms of 3D stacking method and TSV process integration scheme. The permanent and bumpless wafer-to-wafer (PBWW) bonding technology can be applied to the DRAM wafers in the wide-I/O memory cube application. Backside TSV process with its electrical characteristics is also studied. The combination of these two process technologies can further lower the overall process cost and speed up the mass production.

Analyses of printed circuit boards subjected to vibration loadings under various clamping types and reinforced ribs

Electronic systems installed under the dynamic environment such as those on the transportation vehicles, military and aerospace equipment, and handheld mobile devices, are often subjected to harsh vibrations. How to improve the life of these electronic devices is an important issue other than their functional design. In this study, these electronic systems with different installation conditions and vibration loadings, are analyzed for their deformation at each vibration mode. The locations where key electronic components mounted were examined for the resulting stresses. Finally, either the ribs or the special fixtures are designed in reducing the resulting dynamic stresses and thus enhance the systems life. In the experimental study, the Scanning Laser Doppler Vibrometer(SLDV) was used for measuring the dynamic characteristics such as the natural frequencies and the mode shapes of the printed circuit boards (PCB) under various clamping conditions. The resulted displacement can be input to the finite element analysis software or the simplified mathematical model for calculating the stresses in estimating the life. It is quite often that due to circuit design constraints, some electronic components are inevitably mounted on those locations with severe deformation. Thus, it has to use the reinforced ribs to improve the local stiffness of the mounting locations. Furthermore, the wedge lock which is commonly used in avionics was also studied for its effect on the PCB deformation and the solder ball stresses. Through the study, it was found that the vibration resistance of the board equipped the ribs is better than that without the ribs. The stress act on the solder balls of former is less than the latter relatively. Meanwhile, those PCBs with long ribs were better than those of short ribs in vibration resistance. However, the effects of short ribs varies depend on its using conditions. For the clamping with wedge lock, it is much better than other clamping methods in the study since it can reduce the stresses on the solder balls dramatically. The effects can even compete with the boards equipped the long ribs. This might explain why wedge lock is usually used on those important and precise avionic electronic equipments.

Study of TSV filling performance with wide-range pattern densities by using a novel plating chamber with surface paddle agitation

TSV (through silicon via) metallization is one key process in 3DIC integration. Due to high aspect ratio and filling volume, TSV copper plating is the most time-consuming module in the whole process flow. To increase the throughput of electroplating, tool configurations and plating chemistry should be optimized. In this work, an electroplating chamber with a novel paddle design is used in this experiment to study the effects of paddle agitation on plating performance. The influence of this paddle design on different TSV pattern density and geometric scheme are also investigated.