Ralph Halbach

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas, for 1.0V thin oxide devices, gate-oxide breakdown failure occurred

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

The on-resistance and failure current of electrostatic discharge (ESD) protection diodes in 90 nm and 65 nm bulk CMOS technologies is determined largely by the resistance and failure of metal lines, contacts or vias. With design optimization, P/sup +//N-well ESD diodes fabricated in a 90 nm bulk CMOS technology achieved a forward voltage drop of 1.66 V at 2 A, an on-resistance of 0.27 /spl Omega/ and a 100 ns TLP failure current greater than 5 A with a junction capacitance of only 125 fF, area of 330 /spl mu/m/sup 2/ and anode perimeter of 300 /spl mu/m.

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

In this work, the effect of design parameters on the internal and external latchup robustness of dual well (DW) and triple well (TW) test structures designed in 65nm bulk CMOS technology is studied. It is found that while both DW and TW latchup structures were robust for a positive-mode external latchup (latchup trigger current, ITRIG > 200mA), TW latchup structures were more susceptible to negative mode external latchup. The ITRIG for the worst case TW latchup structure was ~50% lower compared to a similarly designed test structure in DW. Isolation of injection sources is more efficient in TW as compared to DW design and can be further improved by appropriate design of I/O devices and guard rings surrounding the I/Os

Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.

Evaluation of ESD characteristics for 65 nm SOI technology

With aggressive scaling and continuous drive for higher performance requirements, electrostatic discharge is becoming a major reliability challenge for advanced integrated circuits. Products must be designed with proper ESD protection circuits to provide adequate robustness and as the limits of the device capability are reached, factors like device reliability due to ESD sensitivity became more critical. In this paper, the ESD characteristics of I/O elements in 65nm SOI technology are thoroughly evaluated. With an appropriate design implementation using these discrete elements, industry standard ESD robustness can be achieved.

I/O Architecture For Improved ESD Protection In Deep Sub-Micron SOI Technologies

In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations show that the reason for change in failure mode is the different current and temperature distribution when the device is operated in bipolar mode due to the presence of ED. The size of the drain silicide blocking can be reduced from 3 to 0.75 μm by the use of ED while keeeping the same ESD failure current with the corresponding area saving benefit. When the ED implant extends under the drain contacts, the on-resistance (Ron) of the device can be reduced by ∼50% with respect to a design where ED is not located under the contacts.

An investigation of ESD protection diode options in SOI

In this article, three SOI ESD diodes were investigated. The standard PB ESD diode with floating polysilicon was found to perform equivalently to the cathode connected version and has similar capacitance. However, the floating version is the preferred solution since the concern of oxide breakdown during an ESD discharge is reduced. The alternative diode formed with the silicide blocking masks warrants further investigation since it has advantages of 20% lower capacitance and the elimination of oxide breakdown issues.

External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies

External latchup phenomena in 65nm CMOS technology under transient events are studied. The effect of different design schemes such as injector to detector spacing, detector orientation, guardring protection strategy and also process factors such as wafer resistivity are investigated. The distance of latchup structures from injector devices inside I/O cells is found to be crucial for the latchup robustness of hardware. Guardring protection strategies with second guardring surrounding the latchup structure are proven to be more robust than that of a single guardring. The substrate resistivity can have a very strong impact to the latchup characteristics of hardware. For distances beyond 5mum between latchup structure and injection device is one of the key factors determining the latchup triggering current levels.