Chung-Chih Wang

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

Key enabling technologies of 300mm 3DIC process integration

Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.

Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications

Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3D IC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.

Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration

Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.

Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

High Endurance Multi-gate TiN Nanocrystal Memory Devices with High-k Blocking Dielectric and High Work Function Gate Electrode

In this work, n-channel Multi-gate FET TiN nanocrystal memory using p+ poly-Si gate and Al2O3 high-k blocking dielectric is demonstrated with good transistor characteristics and moderate high memory window for the first time. High endurance of only 3% window narrowing after 104 P/E cycles is demonstrated. The phenomenon and mechanism of erasing-first induced retention degradation are also reported.

Backside-TSV process development and integration for 2∼3um small size TSV

In this paper, we show the process and integration results of small TSVs integrated by 300mm 3DIC BTSV process. The TSV size is from 2um to 3um (in diameter) with aspect ratio of 10. The achievements of this work are: 1) successful demonstration of 20um thin wafer process by ITRIs 300mm wafer thinning process; 2) 2~3um TSV patterning and etching performed by backside TSV process; 3) Combination of the contact aligner and scanner alignment mark systems to explore the backside process capability of scanner for the first time; 4) Completion of the liner deposition, bottom oxide break and TSV filling of 3um TSV to realize the small size TSV integration; 5) Verification of 3um-diameter and 30um-depth BTSV by daisy chain electrical measurement with the yield of 75% in 1360ea TSV. The result shows the integration feasibility of BTSV with small size TSV for high area penalty concern products.

Low-cost 3DIC process technologies for wide-I/O memory cube

Low-cost 3DIC process approaches are investigated in terms of 3D stacking method and TSV process integration scheme. The permanent and bumpless wafer-to-wafer (PBWW) bonding technology can be applied to the DRAM wafers in the wide-I/O memory cube application. Backside TSV process with its electrical characteristics is also studied. The combination of these two process technologies can further lower the overall process cost and speed up the mass production.

Study of TSV filling performance with wide-range pattern densities by using a novel plating chamber with surface paddle agitation

TSV (through silicon via) metallization is one key process in 3DIC integration. Due to high aspect ratio and filling volume, TSV copper plating is the most time-consuming module in the whole process flow. To increase the throughput of electroplating, tool configurations and plating chemistry should be optimized. In this work, an electroplating chamber with a novel paddle design is used in this experiment to study the effects of paddle agitation on plating performance. The influence of this paddle design on different TSV pattern density and geometric scheme are also investigated.

High-/spl kappa/ HfO2/TiO2/HfO2 multilayer quantum well flash memory devices

High-kappa HfO₂/TiO₂/HfO₂ multilayer quantum well (MQW) charge storage devices with a large memory window of DeltaV_tap8.1 V, an excellent endurance and a good retention (~9% charge loss at 20degC) are reported. Both program and erase speeds of DeltaV_t>3 V@100 mus are achieved for memory transistors under channel hot carrier injections. Furthermore, quantum well memory capacitors with high-kappa Al₂O₃ as a blocking oxide and high work function metal gate show low leakage current density of ~2.4times10^-7 A/cm²@V_g=-5 V at 125degC and high program/erase speed of DeltaV_FB>2 V@10 mus with a low operation voltage of V_g<5 V.