D. Coolbaugh
IBM
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Publication
Featured researches published by D. Coolbaugh.
bipolar/bicmos circuits and technology meeting | 2001
Alvin J. Joseph; D. Coolbaugh; Michael J. Zierak; R. Wuthrich; Peter J. Geiss; Zhong-Xiang He; Xuefeng Liu; Bradley A. Orner; Jeffrey B. Johnson; G. Freeman; David C. Ahlgren; Basanth Jagannathan; Louis D. Lanzerotti; John C. Malinowski; Huajie Chen; J. Chu; Peter B. Gray; Robb Allen Johnson; James S. Dunn; Seshadri Subbanna; Kathryn T. Schonenberg; David L. Harame; R. Groves; K. Watson; D. Jadus; M. Meghelli; A. Rylyakov
A BiCMOS technology is presented that integrates a high performance NPN (f/sub T/=120 GHz and f/sub max/=100 GHz), ASIC compatible 0.11 /spl mu/m L/sub eff/ CMOS, and a full suite of passive elements. Significant HBT performance enhancement compared to previously published results has been achieved through further collector and base profile optimization guided by process and device simulations. Base transit time reduction was achieved by simultaneously increasing the Ge ramp and by limiting the base diffusion with the addition of carbon doping to SiGe epitaxial base. This paper describes IBMs next generation SiGe BiCMOS production technology targeted at the communications market.
bipolar/bicmos circuits and technology meeting | 1999
S. St Onge; David L. Harame; James S. Dunn; Seshadri Subbanna; David C. Ahlgren; G. Freeman; Basanth Jagannathan; J. Jeng; Kathryn T. Schonenberg; Kenneth J. Stein; R. Groves; D. Coolbaugh; Natalie B. Feilchenfeld; Peter J. Geiss; M. Gordon; Peter B. Gray; Douglas B. Hershberger; S. Kilpatrick; Robb Allen Johnson; Alvin J. Joseph; Louis D. Lanzerotti; John C. Malinowski; Bradley A. Orner; Michael J. Zierak
A new base-after-gate integration scheme has been developed to integrate a 47 GHz f/sub t/, 65 GHz F/sub max/SiGe HBT process with a 0.24 /spl mu/m CMOS technology having 0.18 /spl mu/m L/sub eff/ and 5 nm gate oxide. We discuss the benefits and challenges of this integration scheme which decouples the HBT from the CMOS thermal cycles. We also describe the resulting 0.24 /spl mu/m SiGe BiCMOS technology, BiCMOS 6HP, which includes a 7 nm dual gate oxide option and full suite of passive components. The technology provides a high level of integration for mixed-signal RF applications.
bipolar/bicmos circuits and technology meeting | 2002
Natalie B. Feilchenfeld; Louis D. Lanzerotti; David C. Sheridan; Ryan W. Wuthrich; Peter J. Geiss; D. Coolbaugh; Peter B. Gray; J. He; P. Demag; J. Greco; T. Larsen; V. Patel; Michael J. Zierak; Wade J. Hodge; Jay Rascoe; J. Trappasso; Bradley A. Orner; A. Norris; Douglas B. Hershberger; B. Voegeli; Steven H. Voldman; Robert M. Rassel; V. Ramachandrian; Michael L. Gautsch; Ebenezer E. Eshun; R. Hussain; D. Jordan; S. St Onge; James S. Dunn
High frequency performance at low current density and low wafer cost is essential for low power wireless BiCMOS technologies. We have developed a low-complexity, ASIC-compatible, 0.18 /spl mu/m SiGe BiCMOS technology for wireless applications that offers 3 different breakdown voltage NPNs; with the high performance device achieving F/sub t//F/sub max/ of 60/85 GHz with a 3.0 V BV/sub CEO/. In addition, a full suite of high performance passive devices complement the state-of-the-art SiGe wireless HBTs.
bipolar/bicmos circuits and technology meeting | 2004
Louis D. Lanzerotti; Natalie B. Feilchenfeld; D. Coolbaugh; James A. Slinkman; Peter B. Gray; David C. Sheridan; J. Higgins; Wade J. Hodge; M. Gordon; T. Larsen; Michael L. Gautsch; P. Lindgren; R. Murty; Jay Rascoe; K. Watson; T. Stamper; Ebenezer E. Eshun; J. He; K. Downes; Robert M. Rassel; J. Greco; B. Labelle; S. Sweeney; Kenneth J. Stein; R. Bolam; K. Vaed; B. Omer; Alvin J. Joseph; S. St Onge; J. Dunn
We present IBMs next-generation, cost-performance-optimized BiCMOS technology (BiCMOS 8WL) which combines a state-of-the-art suite of SiGe NPNs, foundry compatible 0.13 μm CMOS, and a rich set of modular passive devices. Intended for a wide variety of supply voltages, the technology, features three different performance NPNs and standard, dual oxide, zero V t , and junction isolated FETs. Optimized for wireless and mixed signal applications, BiCMOS 8WL will enable system on a chip integration for 3G cellular applications.
topical meeting on silicon monolithic integrated circuits in rf systems | 2004
Kunal Vaed; Ebenezer E. Eshun; R. Bolam; Kenneth J. Stein; D. Coolbaugh; David C. Ahlgren; James S. Dunn
We demonstrate the simultaneous optimization of 100,000 POH reliability and voltage linearity (<40 ppm/V) for a high-k MIM dielectric (4.5 fF/m/sup 2/) that is both Al and Cu BEOL compatible. Also, we discuss the scaling of dielectric films to achieve excellent bias linearity, while attaining a capacitance density of 7.2 fF/m/sup 2/.
bipolar/bicmos circuits and technology meeting | 2008
Zhong-Xiang He; D. Daley; R. Bolam; D. Vanslette; F. Chen; E. Cooney; D. Mosher; Natalie B. Feilchenfeld; K.M. Newton; Ebenezer E. Eshun; Robert M. Rassel; John J. Benoit; D. Coolbaugh; S. St Onge; James S. Dunn
Two MIM capacitors with capacitance density of 11 and 0.48 fF/um2 were fabricated simultaneously using IBM-s 0.13 um SiGe 8 WL BiCMOS process. Results from DC parametric measurement indicate that these two capacitors compliment each other extremely well.
topical meeting on silicon monolithic integrated circuits in rf systems | 2007
Zhong-Xiang He; M. Erturk; Hanyi Ding; M. Moon; E. Gordon; D. Daley; Anthony K. Stamper; D. Coolbaugh; Ebenezer E. Eshun; M. Gordon; Alvin J. Joseph; S. St Onge; James S. Dunn
High quality factor inductors and highly matched low capacitance density horizontal parallel plate metal-insulator-metal capacitors were fabricated in 130nm RF-CMOS technology with minimal or zero processing step addition. The high quality factor inductors were made using a novel triple damascene integration technique. Peak quality factor of 26 was demonstrated for a 0.3nH inductor. The low capacitance density MIM capacitors were fabricated using standard BEOL copper planes with zero addition of processing steps. Capacitance density value of 0.66 fF/mum 2 was achieved for a six level copper wiring BEOL. Impact of copper plane was characterized to ensure optimal manufacturing production
bipolar/bicmos circuits and technology meeting | 2007
Ephrem G. Gebreselasie; Steven H. Voldman; Zhong-Xiang He; D. Coolbaugh; Robert M. Rassel; T. Kirihata; A. Paganini; C.G. Cox; S.A. Mongeon; S. St Onge; James S. Dunn; R. E. Halbach; J. Lukaitis
electrical overstress/electrostatic discharge symposium | 2005
Steven H. Voldman; Ephrem G. Gebreselasie; Xuefeng Liu; D. Coolbaugh; Alvin J. Joseph
Symposium on ULSI process integration | 2005
S. St Onge; Alvin J. Joseph; Louis D. Lanzerotti; Natalie B. Feilchenfeld; D. Coolbaugh; B. Omer; J. Dunn; D. L. Harame