Eric Duchesne

Underfill selection strategy for Pb-free, low-K and fine pitch organic flip chip applications

The role of underfills is expanding from preserving solder joint reliability to also protecting fragile low-k chip dielectric layers. Traditionally, solder joints required stiff and rigid underfills. Today, low-k layers require more compliant underfill properties. Further complexity comes from the migration to Pb-free solders and changes in chip carrier materials. The myriad of candidates prohibits long term reliability testing of module hardware for every available underfill. A sequential three phase selection strategy is used to characterize and systematically eliminate undesirable candidates and to identify the few favorable underfills that have a high probability of successfully meeting module reliability requirements. The process includes use of industry practices as well as internally developed characterization methods. From an initial list of 20, the selection process identified five underfills for package qualification testing

From Leaded to Lead Free Assembly and New Packaging Technology Challenges

The migration to lead free connections in the microelectronic industry has brought forth many technical challenges, especially in the packaging technology area with respect to materials and processes. The two major drivers to these challenges are the higher melting point and the thermo-mechanical behaviour (less creep than SnPb alloy) of the replacement alloy. The higher melting point drives higher reflow temperatures during the packaging assembly as well as the card assembly and this requires the use of new materials. Higher stresses in the package can result in a reliability impact for the product. The challenge of these lead free related changes is exacerbated by other trends in leading edge organic packaging such as chip low K dielectric materials, larger package and larger chip dimensions and, reduced chip bump pitch. This paper provides the reliability results obtained through various lead free organic package test matrices and qualifications. The principal failure mechanisms are presented and are explained through material properties and finite element modeling studies. Details of the package technology qualification process and results are presented.

Modeling the Flip-Chip Wetting Process

A numerical model is presented for the portion of the flip-chip joining process where liquid-state solder bumps on the substrate and on the device merge (wet) to form full interconnections. An excellent agreement is demonstrated between calculations and experimental data for the accompanying reduction as a function of time in the device-substrate gap height resulting from the wetting process. The model is based on the detailed description of the random wetting transition of every interconnection in large devices, parametrized by a single parameter describing the wetting dynamics of the solder (including, for instance, the retarding effect of oxidation). This allows the model to be used to systematically study the effect of a number of variables (thermal expansion and heating rates, substrate warpage, spatial distribution of solder bump volumes on the substrate and device, etc.) on the rate of occurrence of important defects that appear during the flip-chip wetting process, such as electrical open (nonwet) or short (bridge) defects.

Large-Scale Model of Flip-Chip Joining Defects

A numerical model is developed for the flip chip reflow process, including many significant aspects of the joining dynamics: thermal expansion of the device and substrate; temperature-dependent substrate warpage; random variations of the solder volume with position; and global device position above the substrate. A detailed micro-model of each interconnect captures the transition from two contacting solder bumps to a single continuous solder interconnect, using a random wetting delay parameterized by the surface energy of the bumps relative to an energy scale. The model is shown to correctly fit measurements of the device position during the reflow process, and is used to study the occurrence of non-wet and bridge defects. The effects of spatial variations in the solder volume distribution on these defects is studied in details for an actual device with 12 504 interconnections, using an effective data reduction technique.Copyright

Smart Packaging: A Micro-Sensor Array Integrated to a Flip-Chip Package to Investigate the Effect of Humidity in Microelectronics Package

Lifetime reliability of electronics package is importantfor long term operation of microelectronic devices. Humidity, temperature and resulting strain are three mainreasons for the failure of a flip-chip semiconductor package. For these reasons, continuous research effort have been devotedto integrate moisture, temperature and strain sensorsin package performance and failure risk monitoring. Wehere demonstrate combined humidity, strain and temperaturesensors based on a carbon nanotube mesh embedded in apolyimide matrix. We further demonstrate that an array ofmicro-humidity(/strain/temperature) sensors can be integratedat the wafer finish step of semiconductor chips to provide usefulin-situ real-time information.