E. Van Besien

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry

FinFETs are now widely accepted transistor architecture to replace the two dimensional (2D) metal-oxide-silicon field effect transistors (MOSFETs) into a three dimensional (3D), multi-gate (MG) MOSFETs. The MG FinFETs can be fabricated either on a silicon-on-insulator (SOI) substrate or on a bulk silicon substrate. Both approaches require an advanced patterning not only to improve device performance but also to increase the packing density. Despite the simpler process and the benefit of scaling the fin dimension on an SOI substrate, the Si industry prefers the bulk FinFETS owing to their compatibility with the existing CMOS infrastructure and to the reduced wafer cost. The combination of an advanced patterning such as self-aligned-double-patterning (SADP) and a 1× nm FinFETs device fabrication on a bulk Si substrate poses very challenging geometry constraints for the process integration. In this work, the technical and geometrical challenges of a SADP bulk FinFETs process integration are outlined. Finally, an empirical model to establish robust SADP bulk FinFETs integration is presented.

Through-silicon via technology for three-dimensional integrated circuit manufacturing

Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.

Fundamental study of atomic layer deposition in and on porous low-k films

Atomic layer deposition is a promising technique to deposit conformal, nm-thin metal barriers in high aspect ratio trenches. However, exactly because of its excellent conformality, the deposition can also occur inside the nanopores of the most advanced low-k materials. In this work, the mechanisms of atomic layer deposition on and in low-k, porous dielectric films were studied, using HfO2 as a test material. Exhaustive analyses showed firstly that the HfCl4 precursor penetrated uniformly in the pores throughout a 44 nm low-k film. Secondly it is shown that the pores were sealed as function of precursor size, i.e. there are conditions where the pores became inaccessible for HfCl4, while the - smaller - H2O molecules could still penetrate the pores. From these analyses a deposition model was proposed.

Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography

In this work we integrate an advanced k=2.3 spin-on polymer at 40nm ½ pitch. K-value restoration techniques are investigated and complete k-value restoration is demonstrated using an in-situ HeH2 plasma. An EUV compatible stack and a dielectric dual hard mask scheme is developed to pattern trenches with good uniformity and low litho-etch bias. The impact of scaling the dielectric spacing and of direct CMP on time dependent dielectric breakdown is also studied.