F. Vleugels

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks.

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

In this paper we describe a novel fully self-aligned HBT architecture, which enables a maximum reduction of device parasitics. TCAD simulations show that this architecture is capable of achieving fT/fmax values of 295/425 GHz for an effective emitter area of 0.13times5 mum2. In this new process approach, which is fully CMOS compatible, the collector and base are grown in a single-step non-selective epitaxial process on top of pre-defined bipolar areas. This provides new opportunities for collector-base profile engineering. The collector drift region and the extrinsic base are made self-aligned to the emitter by means of a dry etch that removes all polycrystalline material. The remaining epitaxial pedestal defines the intrinsic device and makes deep trench isolation redundant. We describe the major features of the integration scheme and show measured fT/fmax values of 300/220 GHz on the first fabricated devices with an effective emitter area of 0.13times5 mum2.

A 0.35 /spl mu/m SiGe BiCMOS process featuring a 80 GHz f/sub max/ HBT and integrated high-Q RF passive components

A SiGe HBT, fabricated by means of selective epitaxy, and high-Q RF passive components have been integrated into a 0.35 /spl mu/m BiCMOS process. The HBT features an f/sub T/ of 50 GHz and f/sub max/ of 80 GHz at V/sub BC/=2 V. The npn transistors are integrated in a 0.35 /spl mu/m CMOS process with poly resistors, MIM capacitors and thick metal 4 on chip spiral inductors.

Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology

A 200 GHz F/sub t/ SiGe:C HBT has been integrated into a 0.13 /spl mu/m BiCMOS technology. A previous generation low complexity quasi self-aligned architecture (QSA) is scaled down both in a lateral and vertical way. Lateral sizing is obtained by using present-day step and scan tools. Vertical sizing is achieved by reducing the thermal budget of the active module and by an aggressive scaling of the SiGe:C base epitaxial layer. A deep trench module, featuring a thick oxide liner, has been developed. Excellent DC parameters and peak Ft/Fmax values of 200/160 GHz are demonstrated. The CMOS device characteristics remain unchanged by applying low thermal budget processing in the bipolar module.

Local electrical stimulation of single adherent cells using three-dimensional electrode arrays with small interelectrode distances

In this paper, we describe the localized and selective electrical stimulation of single cells using a three-dimensional electrode array. The chip consisted of 84 nail-like electrodes with a stimulation surface of 0.8 um and interelectrode distances as small as 3 um. N2A cells were used to compare bipolar stimulation between one electrode in- and one outside the cell on the one hand, and two electrodes in the same cell on the other hand. Selective and localized stimulation of primary embryonic cardiomyocytes showed the possibility to use this chip with excitable cells. The response of the cells to applied electrical fields was monitored using calcium imaging whereas assessment of electroporation was determined following influx of propidium iodide. Arrays of these three-dimensional electrodes could eventually be used as a tool to selectively electroporate the membrane of single cells for genetic manipulation or to obtain electrical access to the inner compartment of the cell.

A Novel Deep Trench Isolation Featuring Airgaps for a High-Speed 0.13μm SiGe:C BiCMOS Technology

A novel scheme for deep trench isolation is presented, which uses an airgap as insulator. When incorporated in our 0.13mum SiGe:C BiCMOS technology, the peripheral substrate parasitics decrease with an order of magnitude to a record value of 0.02fF/mum, which significantly improves the device RF performance

A 205/275GHz fT/fmax Airgap Isolated 0.13 m BiCMOS Technology featuring on-chip High Quality Passives

A QSA airgap isolated HBT module, embedded in a 0.13mum BiCMOS technology, reaches fT/fmaxvalues of 205/275GHz and a 3.5ps CML gate-delay. A 17GHz LNA using high quality passives sustains above 8kV HBM ESD stress

Pedestal collector optimization for high speed SiGe:C HBT

An optimized collector doping profile for high-speed SiGe:C HBT devices is presented. A thin and abrupt collector pedestal is implemented in a fT/fMAX 245GHz/460GHz fully self-aligned HBT architecture.

A Novel Isolation Scheme featuring Cavities in the Collector for a High-Speed 0.13μm SiGe:C BiCMOS Technology

A novel isolation scheme is presented in this work, which uses oxide filled cavities in the collector to separate the extrinsic base and collector regions. When incorporated in our 0.13μm SiGe:C BiCMOS technology, a further improvement of the device RF performance is obtained, yielding devices with fT/fmax values of 210/290GHz and 255/210GHz.

A 0.25 /spl mu/m SiGe BiCMOS technology including integrated RF passive components optimised for low power applications

A high performance SiGe HBT has been integrated in a 0.25 /spl mu/m BiCMOS technology optimised for low power applications. A deep trench module is implemented, offering a reduction of the perimeter collector-substrate capacitance by a factor of 5 while at the same time maintaining the wafer surface topography. The in-situ boron doped SiGe profile has been optimised towards a reduction of the base-emitter capacitance. High-quality, low-cost passive components like varactors, high-Q post-processed inductors and highly linear nondispersive MIM capacitors are offered, broadening the low power capabilities of this technology.