T. C. Chai

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

Because of Moores (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21×21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 µm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25×25×0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45×45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

Development of 3-D Silicon Module With TSV for System in Packaging

Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125°C ) and drop test.

Structure Design Optimization and Reliability Analysis on a Pyramidal-Shape Three-Die-Stacked Package With Through-Silicon Via

In this paper, the reliability of a pyramidal-shape three-die-stacked package with through-silicon via (TSV) is studied experimentally and numerically. The initially designed microbumps are located peripherally along the edge of the TSV die, which induces a concentrated bending force on the lower die when the upper die is stacked. Finite-element (FE) simulation results show that such bump layout induces large stress and deflection in the lower die under the die-stacking process. Three-point bend tests were conducted to determine the die strength. Die-stacking experiments were also carried out. The experimental results show that the bottom die cracks when the middle die is stacked and the middle die cracks when the top die is stacked even with a small stacking force. Consistent results have been obtained among FE simulation, die strength bend test, and die-stacking experiments. An optimal bump layout design is proposed, which adds some dummy bumps on the central area of the die to support the bending force induced by the die-stacking process. The optimal design significantly reduces the die stress level and deflection. Finally, a successful die-stacking process is achieved even using a larger stacking force.

Vacuum packaging development and testing for an uncooled IR bolometer device

A vacuum package has been developed for 128/spl times/128 array IR bolometer device with Ge window having anti reflection (AR) coating. For a good vacuum package hermeticity and low out gassing are the two critical elements. A good hermetic sealing has been achieved with Ge window attachment using solder bonding. Different metallization structures have been tried and metallization of oxide/Ti/Ni/Au with additional annealing process was found to have good adhesion and solder wetting. Getters have been activated before final vacuum sealing of the package to absorb the outgassing gases from the packaging materials. Residual Gas analysis (RGA) showed that Thermo electric cooler used inside the package outgassed more compared to other materials. Vacuum inside the package was measured by using a single element IR bolometer device and found to have vacuum of 50milli torr. The developed vacuum package has been tested functionally and found to be no degradation in image before and after packaging.

Design and Optimization of Bump Structures of Large Die Fine Pitch Copper/Low-k FCBGA and Copper Post Interconnections

This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design, metal cracks at RDL were found for the conventional SnAg bump and Cu post samples. In order to improve the bump structure design a thermo-mechanical modeling was performed to identify the effects of different design parameters and to identify the best solution to achieve reliable assembly performance. Simulation has identified few contributing factors: RDL pad thickness, dielectric thickness, UBM via size, UBM size and chip thickness. Then a series of parametric study was performed to identify the set of design points at which the finite element analysis provides the lowest stress level in RDL pad and low-k layer of the chip. Based on the results a guideline for bump configuration is proposed. To confirm the assembly performance of the optimized bump structure, the improved design has been incorporated into final test vehicle, which has a better assembly performance with no RDL pad metal crack found.

Fine pitch copper wire bonding on 45nm tech Cu/low-k chip with different bond pad metallurgy

Wire bonding technology has been widely used in the semiconductor industry for interconnection between device and substrate. Gold wire has been used in industry for many years; however with the increase in the price of gold in the past few years, copper wire has become an alternative. Copper wires have better electrical and thermal performance than gold wire. However due to coppers hardness, the bonding of copper wire to the soft Al bond pad becomes a challenge especially for devices with sensitive and fragile structures underneath the Al bond pad. An optimized Al remnant is required for achieving good reliability [1–2]. A robust bond pad structure with different bond pad material could reduce the impact to structures under the bond pad, minimize Al splash and remove the concern associated with Al remnant for reliability. In this study, copper wire bonding on bond pads with different hardness will be evaluated; they are Al pad and NiPd on top of Al pad. An ASM Eagle Xtreme bonder was used for the study. The forming gas (95%N25%H2) flow rate of 0.4/0.8ℓ per minutes was controlled by a digital flow meter which provides a consistent supply of forming gas. Forming gas maintain an inert environment during the electrode flame-off for free air ball. Capillary with a hole size of 21.6µm, chamfer diameter of 28µm and face angle of 11° was designed for fine pitch bonding with matte surface to enhance the gripping of ball and wire during bonding. A 4N copper with 0.7mil in diameter was used to evaluate the bonding on a Cu/low-k chip with two different bond pad metals with thicknesses of 2.1µm for the Al bond pad and 1.4µm Al/2.5µmNi/0.3µmPd bond pad finish. The NiPd layer used in this study was actually two separate layers which consist of 2.5µm of Ni and 0.3µmPd. Optimized bonding parameters were used on different surfaces to compare the results of bond quality. Comparisons of the deformation of the Al layer and NiPd layer as a result of the bonding was studied. NiPd is harder and could act as a barrier to prevent the direct interaction of the copper wire on the Al bond pad and thus prevent the problems of Al splash especially in fine pitch wire bonding. In this study, target ball size of 34µm were bonded to 55µm bond pad pitch Cu/low-k chips. The effects of the NiPd layer on various parameters were compared with Al bond pad. Evaluated sample were subjected to thermal aging to further understand the effects of temperature on bond quality.

Structural design for Cu/low-K larger die flip chip package

The low-k materials have intrinsically lower modulus and poorer adhesion compared to the commonly used dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of a Cu/low-k larger die flip chip package. Furthermore, underfill selection for a Cu/low-k larger die package is also a challenging issue. In this paper, a two-dimensional finite element analysis was performed on the diagonal cross-section of the package with emphasis on thermally induced stress in low-k layer, inelastic strain in solder bumps and package warpage. A large die flip chip package with 20 times20 mm die size, 150 micron bump pitch on a 45 times 45 mm buildup organic substrate has been undertaken for analysis. A series of parametric study is performed by varying different crucial package dimensions which play an important role in reducing the stress in low-k layer and improve solder fatigue life. Modeling was also performed to select the suitable mechanical properties of underfill, core and buildup layer which can minimize stress in low-k structure and minimize strain in the solder bumps.

Investigation on Die Shift Issues in the 12-in Wafer-Level Compression Molding Process

Die shift issues that arise in embedded wafer-level packaging because of the mold flow process is investigated in this paper, along with solution strategies to address them. The nonlinearity trend of the die shift in the experimental inspection is explained and captured by the numerical simulation with a consideration of the coefficient of thermal expansion effect coupled with the mold flow effect. Optimizing the initial diameter of molding compounds, increasing the thickness of molding compounds, and reducing the filling speed are the three solutions we demonstrate for reducing the drag force. Die shift generated by the mold flow could be reduced by optimizing these controllable parameters.

Modeling and characterization of Cu wire bonding process on silicon chip with 45nm node and Cu/low-k structures

Due to the rapid increase of Au price in recent years, there is an emerging trend to use Cu to replace Au in wire bonding because Cu wire not only has lower cost but also has superior electrical, mechanical and thermal properties. However, Cu ball is much harder than Au ball so that there are several challenges for applying Cu wire bond such as excessive deformation of the Al bond pad and dielectric layer crack under the bond pads, especially for low-k structures. In this study, the stress sensors were designed in the test chips and used to measure under pad stress in real-time. Dynamic finite element modeling methodology was developed for wire bonding process and validated by stress measurement. Parametric studies were conducted using numerical modeling to find ways to reduce Al deformation and stresses by adjusting parameters.

Underfill characterization for multi-layer 3D-SiP stacked chip package

In this paper, evaluation of underfill materials for 3D SiP packages where micro bump interconnections and solder bumps has been presented. Characterization of underfill materials was carried out in terms of adhesion testing on various chip passivation surfaces and process optimization for void free filling. Capillary underfill materials have been evaluated for micro bump interconnections for 3D stacked module with different size chips as well as 3D stacked module with same size chips, and moldable underfill has been evaluated for over molding of stacked module along with underfilling of solder bump interconnections. Die shear test was carried out on adhesion test samples and results revealed failure between chip and polyimide layers in polyimide samples, and mixed failure between underfill and passivation layer in SiN samples. Process optimization for void free underfilling for CUFs were carried out based on dispensing temperature, speed, length, pattern and effects of plasma treatments. For MUF, the transfer molding process optimization was carried out by varying transfer time and die temperature to achieve void free underfilling and molding process. CSAM and through scan analysis was carried out on the under filled samples to check the quality of the underfilling process. The optimized process results shown void free underfilling for both 3D stacked module packages with different size chips as well as same size chips.