Pieter Bex

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

Process characterization of thin wafer debonding with thermoplastic materials

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on extensive characterization of a thermal debonding approach to answer these challenges.

Evolution of temporary wafer (de)bonding technology towards low temperature processes for enhanced 3D integration

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, wafer thinning has become a key element in device processing over the past years. One major criteria, being Total Thickness Variation after thinning, various aspects in the temporary bonding step will be discussed with this respect. While these elements are now becoming mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging and are still prone for evolution.

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down

Among the technological developments pushed by the emergence of 3D-ICs, wafer thinning has become a key element in device processing over the past years. As volume increases, defects in the overall thinning process flow will become a major element of focus in the future. Indeed product wafers arriving at this point of process are of maximum value. Fundamental understanding of the potential defects and their impact on devices is therefore needed to minimize their recurrence.

3D IC assembly using thermal compression bonding and wafer-level underfill — Strategies for quality improvement and throughput enhancement

This paper examines the key aspects for quality improvement and throughput enhancement of thermal compression bonding (TCB) process using dry film laminated wafer-level underfill (WLUF) material. The WLUF material must have good compatibility with pre-assembly and assembly process steps. And all the process steps after and including WLUF lamination have to be co-optimized to ensure the integrity of the WLUF material, consequently leading to higher stacking yield. Good bump joining and underfill filling quality is achieved by optimization different stages of the TCB profiles. A new method enabled by WULF, termed vertical collective bonding (VCB), is applied to multi-layer 3D stacking, producing good bonding quality and significant process time saving. Multi-layer 3D stacks made by the VCB process show good thermomechanical reliability in high temperature storage and thermal cycling tests.

3D stacking cobalt and nickel microbumps and kinetics of corresponding IMCs at low temperatures

To improve the performance of 3D electronic chips, dense I/O and interconnects are required. Increasing the density of interconnects requires smaller pitch micro-bumps. However, when scaling down microbumps several challenges have to be taken into account. Lithography of dense and high aspect ratio bump, wet etching of seed and barrier layer, solder volume and intermetallics (IMC) formation are some of the challenges that needs to be addressed. With reducing bump dimensions, solder volume decreases as well, converting Sn to complete IMC during the Thermo-Compression-Bonding (TCB) process. Full IMC formation increases stress in the joint, leading to crack formation and a brittle connection. Beside concerns about the IMC layer, the UBM (under bump metallization) consumption by the solder has to be addressed as well. Therefore, it is important to select the right UBM and solder to have enough Sn and UBM left in the joint for the time the product is working at a specific temperature [1].

Thermal Compression Bonding: Understanding Heat Transfer by in Situ Measurements and Modeling

Thermal compression bonding (TCB) is becoming an increasingly important process step in the assembly of advanced components such as fine pitch flip chip packages, system-in-package products, and 3D ICs. To increase the throughput and robustness of TCB processes, it is crucial to understand and control important process parameters like time, force and temperature. However, for TCB processes it becomes challenging to measure and control the temperature over the bond interface, since typically different temperature profiles are applied to top chip and substrate. This paper proposes and validates a new methodology for temperature measurements and characterization of heat transfer during a TCB process. On-chip thermal sensors measure the temperature in real time during the TCB process, at different locations on both top and bottom chips. Since the proposed methodology does not require the insertion of a thermocouple in between the top chip and substrate, it will enable more reliable measurements, especially for fine pitch micro bump devices.

A Unique Temporary Bond Solution Based on a Polymeric Material Tacky at Room Temperature and Highly Thermally Resistant Application Extension from 3D-SIC to FO-WLP

Among the technological developments pushed by the adoption of Through Silicon Vias and 3D Stacked IC technologies, wafer thinning on a temporary carrier has become a critical element in device processing over the past years. First generation of adhesive materials enabled the integration of the first devices at the expense of capping the thermal budget. Hence new generation materials are being explored to overcome this limitation and further bring the process complexity down.

On the feasibility of die-to-wafer inorganic dielectric bonding

A feasibility study of die-to-wafer (D2W) bonding of inorganic dielectric layers is conducted on common industrial tools in a typical cleanroom environment. With the help of an additional cleaning step after dicing of the top wafers or using stealth dicing process, 100% bonding success rate from wafers with chemical mechanical polished (CMP-ed) SiO2 has been achieved. Plasma treatment of the top dies has no clear impact on the bonding success rate. However, die shear test shows a significant bonding strength improvement from 10.7±2.6 MPa of samples without pre-bonding plasma treatment to 24.8±9.1 MPa with the treatment. The failure mechanism in the shear test is identified to be fractures in bulk Si, confirming the high bonding strength. The study highlights particle control as the major challenge and current bottleneck in D2W inorganic dielectric bonding. Even in the best experimental split which yields 100% bonding success rate, scanning acoustic microscopy (SAM) and infrared (IR) microscopy show voids in every stack, which are clearly caused by entrapped particles. Cross-sectioning and inspection of the bonding interface by focused ion beam (FIB) show well bonded interfaces between SiO2 layers in the no-void (dark) areas as revealed under SAM, and a narrow gap in the order of tens of nm in the voiding (bright) areas.