M. Tajima

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs

We have investigated what effects randomly oriented and rotated poly-Si gate grains have on lateral carrier profiles in sub-50-nm MOSFETs by direct observations and electrical measurements. Since amorphous gates suppress random channeling penetration of pocket implants, we have increased effective mobility (40%), improved Vth roll-off characteristic (7 nm) and decreased Vth fluctuation (-26%)

Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage

We have experimentally evaluated the effects of the gate line width roughness (LWR) on the electrical characteristics of scaled n-MOSFETs. A larger gate LWR enhances the fluctuation in the subthreshold leakage current in short-channel n-MOSFETs even when the average gate length is maintained. Consequently, suppressing the gate LWR effectively reduces the variability in the threshold voltage of the scaled n-MOSFETs for a high drain voltage.

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process window that comprehensively optimizes both channel strain, induced by eSiGe-S/D (proximity, elevated height, and uniformity), and carrier profiles (offset spacer and thermal budget including millisecond annealing). An optimized eSiGe-S/D with a low thermal budget and amorphous Si gate decreases electrical fluctuations resulting in continuous scaling and a lower manufacturing cost.

Continuous Scaling Methodology of Planar CMOS Transistors by Suppressing Fluctuation in Carrier Profile

The effects of an amorphous Si gate on various electrical fluctuations were evaluated for aggressively scaled CMOS transistors. After developing an advanced amorphous Si gate stack that effectively suppressed gate depletion, we measured intra-wafer fluctuations in gate capacitance and threshold voltage (Vth). The amorphous Si gate decreased intra-wafer fluctuations, intrinsic fluctuations of the scaled transistors, asymmetric fluctuation of the threshold voltage, and fluctuation in threshold voltage mismatch between neighboring transistors in the SRAM. Based on these results, we estimated a yield of the scaled SRAM for 45 nm technology node.

High performance sub-35 nm bulk CMOS with hybrid gate structures of NMOS ; Dopant Confinement Layer (DCL) / PMOS ; Ni-FUSI by using Flash Lamp Anneal (FLA) in Ni-silicidation

We applied flash lamp annealing (FLA) in Ni-silicidation to our developed dopant confinement layer (DCL) structure for the first time. DCL technique is a novel stress memorization technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni fully-silicide (Ni-FUSI) was selectively formed on gates, and both effective work function (WF) control and thinner Teff are improved. On the other hand, unlike pMOS, Ni-FUSI process is not performed in nMOS. Both higher activation of halo and reduction of parasitic resistance in nMOSFET are improved by the combination of DCL structure and FLA in Ni-silicidation. Consequently, the higher drive currents of 1255 muA/mum and 759 muA/mum were obtained Ioff=122 nA/mum and 112 nA/mum at |Vdd|=1.0 V for nMOSFET and pMOSFET, respectively.

Advanced process control for deep sub-100nm gate fabrication

We developed advanced process control (APC); run-by-run model based process control (RbR MBPC) system for deep sub-100nm gate fabrication of CMOS logic ships, designed in order to achieve lot-to-lot variance of gate line width within ±1nm, using critical dimension measurement scanning electron microscope (CD-SEM). Using a lot-mean resist linewidth (pre-etch CD), gate etching plasma condition can be modified to control poly-silicon gate linewidth (post-etch CD) on target. Using etching shift amount of a pilot-wafer within a processing lot, model in the MBPC can be updated to avoid changes of the intercept of the model that is linear equation. The MBPC system was applied to deep sub-100nm gate fabrication and was tested using test lots of 73 to evaluate performance. At an initial lot-mean pre-etch CDs spread of 9.31 nm, the lot-mean post-etch CDs spread was reduced to range of 2.49 nm and its variance was 0.55 nm of 1σ. The range of the linear equation intercept was 8.12 nm and then the range of the prediction errors of feedback control was 2.26 nm, which is originated from both the 1st wafer effect of a pilot wafer of processing lot and measurement CD errors. We found that the prediction error is the largest in errors of the MBPC system. The prediction of model intercept is crucial in the MBPC system in order to achieve lot-to-lot variance of gate line width within ±1nm for gate etching fabrication.