K. Okabe

Advanced channel engineering achieving aggressive reduction of V T variation for ultra-low-power applications

We have achieved aggressive reduction of V<inf>T</inf> variation and V<inf>DD-min</inf> by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V<inf>T</inf> variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V<inf>DD-min</inf> reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

High RF power transistor with laterally modulation-doped channel and self-aligned silicide in 45nm node CMOS technology

A novel high RF power MOSFET was developed to integrate a high-power amplifier into 45 nm node CMOS technology. A self-aligned silicide and laterally modulation-doped channel attained the lowest on-resistance of 1.7 Omega-mm with a high breakdown voltage of more than 10 V and successfully achieved the highest output power density of 0.6 W/mm at the maximum power-added efficiency ever reported among CMOS high breakdown voltage transistors. The reduced gate resistance led to a high frequency characteristic of 43 GHz fmax. We also confirmed that the optimized profile of a gate-overlapped lightly doped drain provides sufficient HC and TDDB reliabilities with a gate oxide as thin as a 3.3 V I/O transistor. These results indicate that a single-chip CMOS transceiver with a high-power amplifier can be produced in advanced CMOS fabs.

High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

This paper demonstrates high performance 35 nm gate length CMOSFETs for 65 nm technology node. The impact of vertical gate scaling on dopant activation in poly-Si gate and device performance is investigated. Total stress controls form both STI and interconnect improved the nMOS drive current up to 5-10% without degradation for pMOS. Excellent controlled 35 nm gate length CMOSFETs are achieved with a high drive current of 650 uA/um for nMOS and 310 uA/um for pMOS at Ioff=70 nA/um at supply voltage of 0.85 V. Low CV/I values of 0.85 ps for nMOS and 1.61 ps for pMOS are obtained. These results are competitive among the latest published data.

Advanced junction profile design scheme by low-temperature millisecond annealing and co-implant for high performance CMOS

We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond extension annealing for pFET was also performed to reduce the parasitic resistance. By combining these technique, an aggressively scaled high-performance bulk CMOS transistors with world competitive nFET and pFET drive currents of 1282/835 muA/mum at 100 nA/mum off-current at Vd = 1 V and Lg = 34 nm respectively, were developed with a conventional poly/SiON gate stack. The developed CMOS transistors not only have high-performance but also manufacturing friendly and cost effective compared with metal/high-k stack devices.

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process window that comprehensively optimizes both channel strain, induced by eSiGe-S/D (proximity, elevated height, and uniformity), and carrier profiles (offset spacer and thermal budget including millisecond annealing). An optimized eSiGe-S/D with a low thermal budget and amorphous Si gate decreases electrical fluctuations resulting in continuous scaling and a lower manufacturing cost.

Lateral extension engineering using nitrogen implantation (N-tub) for high-performance 40-nm pMOSFETs

Lateral extension engineering using a nitrogen-implantation (N-tub) process has enabled high performance 40-nm pMOSFETs that overcome the trade-off between drive current and short channel immunity. The data show that an N dose of above 1/spl times/10/sup 14/ cm/sup -2/ effectively suppresses B diffusion, especially in the lateral extension tail. As a result, we realized a 13% improvement in CV/I from conventional process.

Carrier profile designing to suppress systematic V th variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects

We directly measured that anisotropic dopant diffusion into the shallow trench isolation (STI) sink was the predominant factor to cause dependence of the threshold voltage (Vth) on the active width along the channel direction (LOD) for the nMOSFETs. We evaluated by Raman spectroscopy and 3-D stress simulation effects of the STI-induced stress variation on the Vth. Moreover, we directly measured that dopant diffusions coupled with point defect, as transient enhanced diffusion, resulted in the carrier profile depending on the LOD. In particular, it was found that the excess point defect in the deep source/drain enhanced the random extension edge roughness and increased intrinsic Vth fluctuation in the narrow-LOD nMOSFET.

Successful integration scheme of cost effective dual embedded stressor featuring carbon implant and solid phase epitaxy for high performance CMOS

We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in this scheme since we can independently control both damage and stressor. Second, Ge PAI prior to carbon I/I is also performed to realize a steep carbon profile. Third, the embedded Si:C is required to be positioned beneath the Rp of n+dopant to maximally utilize the low resistance deep SD I/I region. Finally, optimizing thermal budget enables us to suppress both carbon clustering and residual defects induced by Ge PAI without a degradation of Vth-rolloff characteristics and a strain relaxation in embedded SiGe (eSiGe) in PMOSFETs. By using this scheme, we have controlled both parasitic resistance and junction leakage current simultaneously. In addition, UV-Raman spectroscopy and HR-XRD clarified the achievement of more than 1 at% effective substitutional carbon concentration by this scheme. Consequently, a 5.1% improvement in Ion of NMOSFETs for Ioff = 100 nA/µm at Vd = 1.0 V and Ion = 1154 µA/µm was obtained. For PMOSFETs, thanks to an optimized annealing process, strain relaxation in eSiGe was avoided, and thus Ion = 818 µA/µm for Ioff = 100 nA/µm at Vdd = 1.0 V, was obtained. We have successfully demonstrated the CMOS integration with a cost-effective “dual” embedded stressor.

High performance sub-35 nm bulk CMOS with hybrid gate structures of NMOS ; Dopant Confinement Layer (DCL) / PMOS ; Ni-FUSI by using Flash Lamp Anneal (FLA) in Ni-silicidation

We applied flash lamp annealing (FLA) in Ni-silicidation to our developed dopant confinement layer (DCL) structure for the first time. DCL technique is a novel stress memorization technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni fully-silicide (Ni-FUSI) was selectively formed on gates, and both effective work function (WF) control and thinner Teff are improved. On the other hand, unlike pMOS, Ni-FUSI process is not performed in nMOS. Both higher activation of halo and reduction of parasitic resistance in nMOSFET are improved by the combination of DCL structure and FLA in Ni-silicidation. Consequently, the higher drive currents of 1255 muA/mum and 759 muA/mum were obtained Ioff=122 nA/mum and 112 nA/mum at |Vdd|=1.0 V for nMOSFET and pMOSFET, respectively.