Harold W. Kennel

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5×1012 cm−2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE < 40 Å, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.

Technology options for 22nm and beyond

This paper explores the challenges facing the 22nm process generation and beyond. CMOS transistor architectures such as ultra-thin body, FinFET, and nanowire will be compared and contrasted. Mobility enhancements such as channel stress, alternative orientations, and exotic materials will be explored. Resistance challenges will be reviewed in relation to key process techniques such as silicidation, implantation and anneal. Capacitance challenges with traditional and new architectures will be discussed in light of new materials and processing techniques. The impact of new transistor architectures and enhanced channel materials on traditional junction engineering solutions will be summarized.

Modeling Silicon Implantation Damage and Transient Enhanced Diffusion Effects for Silicon Technology Development

Despite more than 20 years of effort, detailed understanding of defect-coupled dopant diffusion in silicon still falls short of what is practically required to support state-of-the-art silicon technology development. The challenge for modeling in industry is to combine the best of our physical understanding with measurements of dopant profiles for technology-relevant conditions to provide models which are as predictive and efficient as possible. This paper presents experimental results which provide insight into damage generation and annealing processes and discusses practical modeling approaches to support technology development despite our incomplete understanding of the physical processes involved.

Kinetics of Shallow Junction Activation: Physical Mechanisms

Forming highly active shallow junctions is a key component enabling low external resistance and high transistor performance. Millisecond flash or scanning laser anneals can be used to contain diffusion and optimize activation, either directly by leveraging temperatures exceeding 1200C, or in combination with non-equilibrium processes such as amorphization plus solid phase epitaxy or liquid phase epitaxy. Diffusionless profiles can be obtained, but may not be optimal for devices. Consideration of deactivation physics is crucial to incorporation of any process leveraging superactive doping, since relaxation of doping is frequently very rapid, and may be crucially influenced by implant damage effects. Developing an understanding of dominant mechanisms is essential for the exploitation of millisecond or faster anneals to form superactive doping

Ab-initio calculations to predict stress effects on defects and diffusion in silicon

Stress effects play an increasing role in processing and performance of current nanoscale ULSI devices. In this paper, we show how first principle calculations can be used to predict stress effects on equilibrium concentration and diffusion of defects in silicon. The method used is capable of treating arbitrary strain states, which is an extension beyond the hydrostatic case. For biaxial strain, we find strongly anisotropic diffusion of interstitials. We also extended our analysis to B and found similar behavior, leading to the prediction of enhanced lateral diffusion in strained Si on SiGe structures.

Modeling of ultrahighly doped shallow junctions for aggressively scaled CMOS

This paper presents an integrated modeling approach to address diffusion and activation challenges in sub-90 nm CMOS technology. Co-implants of F and Ge are shown to reduce diffusion rates and a new model for the interactive effects is presented. Complex codiffusion behavior of As and P is presented and modeling concepts elucidated. Tradeoffs such as sheet resistance for a given junction depth, and how these depend on impurities, as well as soak vs. spike rapid thermal anneals (RTA), can be understood with simulation models.

Molecular dynamics modeling of solid phase epitaxial regrowth

Solid phase epitaxial regrowth (SPER) is of great technological importance in semiconductor device fabrication. A better understanding and accurately modeling of its behavior are vital to the design of fabrication processes and the improvement of the device performance. In this paper, SPER was modeled by molecular dynamics (MD) with Tersoff potential. Extensive MD simulations were conducted to study the dependence of SPER rate on temperature, growth orientation, pressure, and uniaxial stress. The simulation data were fitted to empirical formula, and the results were compared with experimental data. It was concluded that MD with Tersoff potential can qualitatively describe the SPER process. For a more quantitatively accurate model, larger simulation systems and a better interatomic potential are needed.