Heui-Seung Lee

Highly thermal robust NiSi for nanoscale MOSFETs utilizing a novel hydrogen plasma immersion ion implantation and Ni-Co-TiN tri-layer

In this letter, hydrogen plasma immersion ion implantation (H PIII) with Ni-Co-TiN tri-layer is introduced for the first time to enhance the thermal stability of the Ni-silicide for nanoscale CMOS technology. The Ni-silicided poly-Si gate and source/drain showed stable sheet resistance in spite of 650/spl deg/C, 30 min post-silicidation annealing. The junction leakage current is even improved a lot without degradation of device performance using the proposed method.

On-chip charge pumping method for characterization of interface states of ultra thin gate oxide in nano CMOS technology

For the first time, on-chip charge pumping method is proposed to characterize ultra thin gate oxide for nano-scale CMOSFETs. Designed on-chip charge pumping system can supply 30-500MHz square-type pulse waves to DUT transistor and measured charge pumping current showed no gate tunneling current dependency which can be easily monitored in very thin gate oxide. In addition to the measurement of interface states by fixed-amplitude method, the distribution of interface states in channel region can be easily extracted by fixed-base method using this system. The proposed method is also successfully applied to analyze hot-carrier stress-induced threshold voltage (Vt)-degradation and to evaluate plasma process induced damage in terms of interface trap density

Co-Induced Low-Temperature Silicidation of Ni Germanosilicide Using NiPt Alloy and the Effect of Ge Ratio on Thermal Stability

In this paper, novel Ni germanosilicide technology using NiPt alloy and Co overlayer has been proposed. Using the Co overlayer after NiPt deposition on Si1-xGex, the formation temperature of low resistive Ni germanosilicide is lowered with high thermal stability. The thermal stability of Ni germanosilicide with different Ge fraction in is also characterized. The sheet resistance degrades as increasing the Ge fraction (x) in Si1-xGex when NiPt/TiN is used. However, using the Co overlayer, the sheet resistance property among Ni germanosilicide formed with different Ge fraction is improved greatly compared with those of NiPt/TiN case (without Co overlayer). Therefore, low-temperature formation of highly thermal robust Ni germanosilicide can be achieved through the NiPt/Co/TiN tri-layer.

Investigation of Device Performance and Negative Bias Temperature Instability of Plasma Nitrided Oxide in Nanoscale p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor's

In this paper, we investigated the device performance and negative bias temperature instability (NBTI) degradation for thermally nitrided oxide (TNO) and plasma nitrided oxide (PNO) in nanoscale p-channel metal oxide semiconductor field effect transistor (PMOSFET). PNOs show the improvement of dielectric performance compared to TNO with no change of the device performance. PNOs also show the improvement of NBTI immunity than TNO at low temperature stress, whereas NBTI immunity of PNO with high N concentration can be worse than TNO at high temperature stress. Recovery effect of NBTI degradation of PNO is lower than that of TNO and it is increased as the N concentration is increased in PNO because the dissociated Si dangling bonds and generated positive oxide charges are repassivated and neutralized, respectively. Moreover, complete recovery of ΔVth is dominated by neutralization of positive oxide charges. Therefore, N contents at polycrystalline Si/SiO2 interface as well as N contents at Si/SiO2 interface can affect significantly on NBTI degradation and recovery effect.

Optimal Ni/Co thickness extraction and two step rapid thermal process of the nickel-silicide for nanoscale complementary metal oxide semiconductor (CMOS) application

NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.

Novel test structures for on-chip characterization of coupling capacitance variation by in- and anti-phase crosstalk in multi-level metallization

Novel test structure is proposed for on-chip evaluation of the crosstalk-induced variation of coupling capacitance in multi-fanout and global interconnect lines. Then, it is experimentally shown that the crosstalk-induced variation of coupling capacitance, /spl Delta/C/sub C/ can be larger than the static coupling capacitance, C/sub C/ for both multi-fanout and global interconnect using the novel on-chip test structures. HSPICE simulation is performed to confirm the experimental data.

New Observation of NBTI Degradation and Recovery Effect of Plasma Nitrided Oxide in Nano Scale PMOSFET's

Oxide in Nano Scale PMOSFET’s In-Shik Han, Hee-Hwan Ji, Tae-Gyu Goo, Ook-Sang You, Won-Ho Choi, Min-Ki Na, Ga-Won Lee, Yong-Goo Kim, Sung-Hyung Park, Heui-Seung Lee, Young-Seok Kang, Dae-Byung Kim and Hi-Deok Lee Dept. of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea Phone: +82-42-821-6868, Fax: +82-42-823-9544, *E-mail: hdlee@cnu.ac.kr Magnachip Semiconductor Inc., Hungduk-gu, Cheongju, Choongbuk, 361-725, Korea

Dependency of the Device Characteristics on Plasma Nitrided Oxide for Nano-scale PMOSFET

In this paper, the reliability (NBTI degradation: ) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

Dependence of Analog and Digital Performances on Mechanical Film Stress of ILD Layers in Nanoscale CMOSFETs

In this study, film-stress-induced device performance variation is characterized in terms of digital and analog performances. Interlayer dielectric (ILD) layers such as PECVD Si3N4 and LPCVD SiON with different stress-affected saturation currents and off-state leakage currents are investigated extensively. To further analyze stress effects, the film stress of PECVD Si3N4 is varied from compressive stress to tensile stress. It is shown that tensile stress improved NMOS performance through the decrease of interface state density (Dit) and the increase of carrier mobility. In the case of PMOS with highly tensile stress, the mobility is decreased due to the increase of Dit. The oxide fixed charge Qf of PMOS is also reduced evidently by the tensile stress film.

Highly thermal robust Ni-germanosilicide utilizing NiPt/Co/TiN tri-layer for CMOS application

Highly thermal robust Ni-germanosilicide has been developed using the novel NiPt/Co/TiN tri-layer. Ni-germanosilicide properties were characterized with different source/drain dopants and Ge concentrations for nanoscale CMOSFETs application. The sheet resistance was degraded as the Ge concentration increases in Si/sub 1-x/Ge/sub x/. Low temperature silicidation and wide range of RTP process window are achieved as well as the improvement of the thermal stability according to different dopant types by the subsequent Co and TiN capping layer above NiPt on Si/sub 1-x/Ge/sub x/.