Yoshiaki Yoshihara

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications

The fisrt 77 GHz frequency modulated continuos wave (FMCW) radar transceiver IC with an accurate FMCW signal generator using a 90 nm CMOS process is presented. To realize accurate FMCW radar system in CMOS, a PLL synthesizer that is able to output linear FMCW frequency is applied. Measured radar performances, output spectrum and distance of a target, show the transceiver achieves a fundamental function for radar applications.

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS

A 60-GHz phase-locked loop (PLL) with inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mum2. The active area of the PLL is 0.6 x 0.6 mm2.

A 60-GHz CMOS Receiver with Frequency Synthesizer

A 60-GHz receiver (RX) chip fabricated in 90 nm CMOS process is reported. The RX chip consists of an LNA, a downconversion mixer and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz. These results indicate the possibility of realization of CMOS single-chip 60-GHz transceiver.

A 60-GHz CMOS power amplifier with Marchand balun-based parallel power combiner

A novel Marchand balun-based parallel power combiner suitable for a 60-GHz CMOS power amplifier is proposed. It improves the power efficiency by solving the issues of the phase difference of the signals to be combined and the low coupling factor of the on-chip balun in scaled CMOS technologies. The power amplifier using the proposed power combiner is fabricated in a 90 nm CMOS process with 1.2 V supply. Measured power gain, output referred 1-dB compression point, and saturated output power are 11.2 dB, +8.3 dBm, and +11.2 dBm, respectively, at 60-GHz.

A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control

A low-voltage, low-power class-D VCO is presented. An LDO based dynamic supply voltage control technique for the class-D VCO is proposed, which realizes fast and reliable start-up and extremely low-voltage operation of the class-D VCO. The proposed LDO-VCO is fabricated using a 28 nm CMOS technology. The measured phase noise is -115.9 dBc/Hz at 1 MHz offset from the 2.35 GHz carrier, while drawing the current of 760 μA from 0.5 V LDO input. The class-D VCO core consumes 0.171 mW from 225 mV LDO output and the FoM is 191.0 dBc/Hz.

A 65nm CMOS, 1.5-mm Bluetooth transceiver with integrated antenna filter for Co-existence with a WCDMA transmitter

This paper presents a fully integrated Bluetooth transceiver in a 65 nm CMOS, which occupies 1.5 mm2 on the chip. It even integrates an antenna filter to reject blocker from the co-existing wireless system such as WCDMA and GSM. The frequency response of the antenna filter is controlled by an onchip temperature monitor. The antenna filter achieves 30 dB rejection over the entire WCDMA band-I of 1920-1980 MHz with the temperature range from -40 to 80 °C. The transceiver achieves RX sensitivity of -89.1 dBm and TX output level of +4 dBm.

An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS

As single-chip implementation of Bluetooth transceivers gains popularity [1,2], area reduction in the analog/RF part is inevitable. While all-digital polar transmitters achieving a small die size are attracting attention and their application to Bluetooth Basic Rate and GSM standards is now the reality [3,4], due to their shortcoming in the modulation accuracy above their loop bandwidth, it is very difficult to apply it to non-constant envelope modulations. This paper reports on a polar transmitter that is capable of 8-DPSK modulation for the Bluetooth EDR standard. It implements the second-order approximation scheme in the gain calculation of the DCO and a phase rotation-constant digital PA. It achieves DEVM of 6.1% at 0dBm output in sending 8-DPSK signal for Bluetooth EDR, drawing 35mA from a 1.2V supply and occupies 0.75×0.75mm2.

All-digital single-inductor multiple-output DC-DC converter with over 65.3% efficiency in 1 uW to 50 mW load range and 86.3% peak efficiency

This paper presents a wide load range all-digital single-inductor multiple-output (SIMO) DC-DC buck converter. Since sensor nodes for the Internet of Things (IoT) operate mostly in a standby mode and occasionally in an active mode, a SIMO DC-DC converter supporting a wide load range with practical conversion efficiency is required. In order to achieve practical efficiency in a wide load range, three new techniques of a maximum-on-time control, a channel-consolidated-multiple-switching and a logic-gate-based zero-current-detection circuit are proposed. The proposed SIMO DC-DC converter achieves 86.3% peak efficiency and the wide load range from 1 uW to 50 mW with over 65.3% efficiency. This is the first SIMO DC-DC converter with over 60% efficiency in such a wide load range.