Kazumi Kurimoto

A new half-micron p-channel MOSFET with LATIPS (large-tilt-angle implanted punchthrough stopper)

A novel half-micron buried p-MOSFET with a large-tilt-angle-implanted punchthrough stopper (LATIPS) is proposed. The n/sup +/ LATIPs region is successfully realized adjacent to the p/sup +/ source/drain, even without a sidewall spacer, by taking advantage of the n/sup +/ large-tilt-angle implant. In spite of the relatively deep p/sup +/ junction of 0.2- mu m depth and the low n-well concentration of 1*10/sup 16/ cm/sup -3/, the 0.5- mu m LATIPS device achieves high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/dec, with a high transconductance of 135 mS/mm and small body effect. The submicron LATIPS device also achieves improved resistance to hot-electron-induced punchthrough as compared with the conventional device. The LATIPS technique is most promising for half-micron CMOS (complementary MOS) ULSIs (ultra-large-scale integrated circuits).<<ETX>>

Anomalous TDDB Statistics of Gate Dielectrics Caused by Charging-Induced Dynamic Stress Relaxation Under Constant–Voltage Stress

Anomalous Time Dependent Dielectric Breakdown (TDDB) statistics of thick gate dielectrics, i.e., too large stress field/voltage dependence and nonlinear Weibull plot of TDDB lifetime, have been observed. Through the analysis of behaviors under the TDDB stress and also the comparison with thin gate dielectrics, it has been revealed that just the intrinsic charging of injected carriers to initial and stress-generated defects induces the dynamic stress relaxation under the constant-voltage stress, resulting in anomalous TDDB statistics. This charging-induced dynamic stress relaxation (CiDSR) effect reduces the validity of well-known Weibull statistics and prevents us from accurately predicting TDDB lifetimes utilizing various conventional scaling procedures, such as area, failure rate, and temperature scaling. Impact of the CiDSR effect increases with the thickness of gate dielectrics and the development of an appropriate lifetime prediction method is urgent not only for Si devices but also for various compound devices having thick gate dielectrics, such as GaN and SiC power devices.

Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices

The effect of the gate to drain capacitance on low voltage operated CMOS devices is investigated. It is found that the Miller and feed-forward effects are enhanced with the reduction of the supply voltage. The reduction of the gate overlap capacitance as well as the threshold voltage and junction capacitance is a key issue to achieve high speed circuit operation at low supply voltage. We propose a low power, high speed T-gate CMOS device with dual gate structure using an amorphous-Si/poly-Si layer. A new process scheme is proposed to prevent boron penetration and to fabricate the T-gate structure effectively. It is found that the new T-gate CMOS with dual gate structure reduces the gate to drain overlap capacitance maintaining high current drivability at low power-supply voltage.

An electrothermal circuit simulation using an equivalent thermal network for electrostatic discharge (ESD)

This paper describes an electrothermal circuit simulation using an equivalent thermal network for electrostatic discharge (ESD). Electrothermal transient characteristics in ESD protection devices are clarified in detail by modeling of complicated snapback behavior and thermal modeling in the multiple layer. The new model allows the simulation for the damage region and failure thresholds of n-MOSFETs under ESD stress conditions.<<ETX>>