Hsien-Nan Chiu

Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 84%) and the retention time (∼ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 72%) and the retention time (∼ 50%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

Advanced block oxide MOSFETs for 25 nm technology node

This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature; bMOS shows about 40% lower temperature compared with the bMPI. However, the bMPI can gain better short-channel behavior due to the BOX under its channel layer. In addition, although the drain on-state current of the bMPI is lower than that of the bMOS, the lower leakage current helps to gain a higher ION/IOFF ratio. It is a trade-off between performance and reliability. Additionally, if the fabrication cost is also considered, the bMOS will exhibit better advantage than the bMPI because of a bulk wafer being used for a starting substrate.

Thermal characteristics of an advanced bMPI-based 1T-DRAM cell

In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.

Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length

In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the common electrodes areas are shared, the layout area can be reduced more than 71%, which leads to significantly increase on the packaging density of CMOS circuits.

A novel self-align double gate MOSFET with source/drain tie

In this paper, a novel device architecture, namely novel self-align double gate MOSFET with source/drain tie, is proposed and compared with the ITRS. According to the simulation results, our proposed transistor not only enhances the on/off current ratio, but also decreases the drain induced barrier lowering and subthreshold swing due to the double gate scheme structure.

A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications

We present a reliability analysis of a new vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM applications. The proposed 1T-DRAM device can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved by about 95% when compared to the planer bMPI 1T-DRAM. Owing to the double-gate structure, vertical bMPI has great gate controllability over the channel region; hence, it can reduce the short-channel effects (SCEs) and enhance the current drive. And the VbMPI 1T-DRAM cell can keep holes in nature body region, which leads to an increase in data retention time.

The impact of junction depth on vertical sidewall MOSFETs with embedded gate

According to the numerical simulations, the EGVMOS w/ LDD process is a choice for obtaining both the reduced SCEs and lower Cgd value. However, the degraded Ids-Vds characteristic curves are not desired as a result from the floating-body effects. Therefore, a tradeoff between good control of SCEs and kink-free is shown. Although the EGVMOS w/o LDD process shows slightly degraded C-V and short-channel characteristics, the results are acceptable. Moreover, the EGVMOS w/ 2.5 nm Si etching after gate formation is also good for decreased Cgd due to the offset structure.