Chih-Hung Sun

Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 84%) and the retention time (∼ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

Advanced block oxide MOSFETs for 25 nm technology node

This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature; bMOS shows about 40% lower temperature compared with the bMPI. However, the bMPI can gain better short-channel behavior due to the BOX under its channel layer. In addition, although the drain on-state current of the bMPI is lower than that of the bMOS, the lower leakage current helps to gain a higher ION/IOFF ratio. It is a trade-off between performance and reliability. Additionally, if the fabrication cost is also considered, the bMOS will exhibit better advantage than the bMPI because of a bulk wafer being used for a starting substrate.

Design theory and fabrication process of 90nm unipolar-CMOS

The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility III–V and CNT based technology. According to the measurement two empirical models, the new concept of the load line drawing and the optimum design of the unipolar-CMOS are also illustrated. Employing them for unipolar-CMOS design, the desired high performance ultimate SOC and SOP system can be easily realized.

Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length

In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the common electrodes areas are shared, the layout area can be reduced more than 71%, which leads to significantly increase on the packaging density of CMOS circuits.

A novel self-align double gate MOSFET with source/drain tie

In this paper, a novel device architecture, namely novel self-align double gate MOSFET with source/drain tie, is proposed and compared with the ITRS. According to the simulation results, our proposed transistor not only enhances the on/off current ratio, but also decreases the drain induced barrier lowering and subthreshold swing due to the double gate scheme structure.

A unipolar-CMOS with recessed source/drain load

In this study, for the first time, we produce a unipolar-CMOS logic, by replacing each of the PMOS devices with a gate-controlled punchthrough NMOS. Such a new logic maintains the traditional advantages of CMOS fabrication while avoiding the need to fabricate large p-well region on chip; this can lead to an improved transistor density, especial in non-Si technologies. To validate the feasibility of this design theory, we use commercial TCAD tools to simulate and verify Unipolar-CMOS inverters, NAND gates, NOR gates, and static random-access memory (SRAM). In each case, the simulation results show that the Unipolar-CMOS logic functions correctly. Moreover, this new logic is scalable to the Deca-Nanometer range, because the gate-controlled punchthrough NMOS is not significantly affected by the short channel effect. Owing to its superior integration-density and fabrication process, the Unipolar-CMOS technology can not only maintain but also go beyond the Moores law.

The impact of junction depth on vertical sidewall MOSFETs with embedded gate

According to the numerical simulations, the EGVMOS w/ LDD process is a choice for obtaining both the reduced SCEs and lower Cgd value. However, the degraded Ids-Vds characteristic curves are not desired as a result from the floating-body effects. Therefore, a tradeoff between good control of SCEs and kink-free is shown. Although the EGVMOS w/o LDD process shows slightly degraded C-V and short-channel characteristics, the results are acceptable. Moreover, the EGVMOS w/ 2.5 nm Si etching after gate formation is also good for decreased Cgd due to the offset structure.

Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate

We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional VMOS.

Characteristics of a Local Oxidation of silicon multi-tie body polysilicon thin-film transistor

This paper is to investigate the novel features of a Local Oxidation of silicon multi-tie body polycrystalline silicon thin-film transistor (LOCOS MTB poly-Si TFT) by using numerical simulations. Based on the results, our proposed TFT have improved reliability due to the presence of the LOCOS MTB scheme. Although a multi-body-tied scheme is not compatible in current TFT process, it is believed that this study can help us understand the influence of body-tied scheme on the properties of poly-Si TFT.

A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs

This paper aims to investigate the performance and reliability trade-off of the self-aligned (SA) π-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) field-effect transistors (FETs). Based on the simulations, the S/D-tie effects are crucial to the future of quasi-SOI devices. The preliminary results of electrical characteristics of the SA-πFETs are carefully demonstrated.