Chih-Hao Kuo

Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 84%) and the retention time (∼ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure

In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.

Advanced block oxide MOSFETs for 25 nm technology node

This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature; bMOS shows about 40% lower temperature compared with the bMPI. However, the bMPI can gain better short-channel behavior due to the BOX under its channel layer. In addition, although the drain on-state current of the bMPI is lower than that of the bMOS, the lower leakage current helps to gain a higher ION/IOFF ratio. It is a trade-off between performance and reliability. Additionally, if the fabrication cost is also considered, the bMOS will exhibit better advantage than the bMPI because of a bulk wafer being used for a starting substrate.

Design theory and fabrication process of 90nm unipolar-CMOS

The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility III–V and CNT based technology. According to the measurement two empirical models, the new concept of the load line drawing and the optimum design of the unipolar-CMOS are also illustrated. Employing them for unipolar-CMOS design, the desired high performance ultimate SOC and SOP system can be easily realized.

Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length

In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the common electrodes areas are shared, the layout area can be reduced more than 71%, which leads to significantly increase on the packaging density of CMOS circuits.

A novel self-align double gate MOSFET with source/drain tie

In this paper, a novel device architecture, namely novel self-align double gate MOSFET with source/drain tie, is proposed and compared with the ITRS. According to the simulation results, our proposed transistor not only enhances the on/off current ratio, but also decreases the drain induced barrier lowering and subthreshold swing due to the double gate scheme structure.

Electrical Characterization of 10-nm π-Shaped S/D MOSFETs

In this paper, we numerically explore electrical characteristics of a simple device called the π-shaped source/drain (π-S/D) MOS transistor. Some techniques such as Si/SiGe epitaxial growth and selective SiGe etch process are implemented for the fabrication of quasi-SOI devices with an S/D tie. More importantly, a new method presented here for fabricating π-S/D MOSFETs does not require any additional mask step due to self-alignment process being exploited. The isolation technique is carried out only after S/D annealing, resulting in only four extra process steps introduced in this new quasi-SOI technology. According to numerical simulations, the new π-S/D structure has better control on the short-channel and thermal effects compared with the conventional (conv.) π-S/D structure. Despite Miller capacitance sacrifice behaviour owing to the absence of the conv. isolation approach before gate definition, which causes an increase in the body area under the gate, NMOSFET intrinsic delay τ and cutoff frequency f T are within acceptable limits for this new structure.

Characterisation of new vertical MOSFETs with recessed gate

This study presents a new vertical MOSFET with recessed gate (RG). Based on the TCAD simulation results, our proposed VMOS structure can gain reduced parasitic capacitance (compared to the conventional VMOS, both Cgd and Cgs can be reduced about 12% and 38.78%, respectively at VDs =1.0 V), improved drain saturation current, and free kink characteristics, in comparison to a conventional VMOS structure. Moreover, the short-channel characteristics of RGVMOS which is modified from the EGVMOS are still acceptable. Most importantly, the manipulation of fabricating this newly proposed structure is enhanced mainly owing to the semicircle gate scheme.

An ultimate planar MOS transistor for high-performance applications based on classical and modern techniques

An ultimate n-shaped source/drain (π-S/D) metal-oxide semiconductor (MOS) transistor is proposed in this paper. The method used to fabricate the proposed π-S/D transistor is based on both the classical and modern techniques (such as, Si-SiGe epitaxial growth, selective SiGe removal, etc.) that can be controllable and repeatable. Also, a new and simple process without the need of an additional mask to achieve the self-aligned (SA) π-S/D structure is demonstrated and its preliminary characteristics are investigated through three dimensional (3D) numerical simulations.

A new buried-gate VMOSFET with suppressed overlap capacitance and improved electrical characteristics

This study presents a new buried-gate vertical MOSFET (BGVMOS) with suppressed overlap capacitance and improved electrical characteristics due to its modified gate structure. According to the TCAD simulations, our proposed BGVMOS structure can gain reduced parasitic capacitances (27.11% Cgd and 37.53% Cgs at VDs = 1.0 V), improved drain saturation current, and free kink effect, in comparison to a conventional VMOS (CVMOS) structure. Most importantly, the reduced surface scattering in the BGVMOS helps improve the drain current and the transconductance mainly owing to the 1/4 circle gate scheme which is difficult task for a CVMOS transistor.