Tzu-Feng Chang

Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 84%) and the retention time (∼ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 72%) and the retention time (∼ 50%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

Characteristics of a Smiling Polysilicon Thin-Film Transistor

One-transistor dynamic random access memory (1T-DRAM) thin-film transistor (TFT) could lead the revolution of system-on-panel application. However, no useful 1T-DRAM is fabricated on the polysilicon (poly-Si) thin film up to now. In this letter, we present a novel method to fabricate a smiling poly-Si TFT for 1T-DRAM applications. The experimental results show that the short-channel effects can be reduced because the smiling scheme is used to suppress the charge sharing and the source/drain-tied scheme can help to overcome the self-heating. Moreover, the device fabrication is fully compatible with current complementary metal-oxide-semiconductor (CMOS) technology.

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

Advanced block oxide MOSFETs for 25 nm technology node

This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature; bMOS shows about 40% lower temperature compared with the bMPI. However, the bMPI can gain better short-channel behavior due to the BOX under its channel layer. In addition, although the drain on-state current of the bMPI is lower than that of the bMOS, the lower leakage current helps to gain a higher ION/IOFF ratio. It is a trade-off between performance and reliability. Additionally, if the fabrication cost is also considered, the bMOS will exhibit better advantage than the bMPI because of a bulk wafer being used for a starting substrate.

A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

This paper presents a three-dimensional (3D) simulation study of source/drain (S/D)-tied (SDT) double-gate (DG) fin field-effect transistor (FinFET) design for 16-nm half-pitch technology generation and beyond using technology computer-aided design (TCAD) tools. A simple process to fabricate the proposed SDT FinFET is proposed. An investigation of the fin width (Wfin) on the electrical characteristics is shown, suggesting that a reduced Wfin is good for both the suppression of short-channel effects and the reduction of parasitic capacitance in SDT FinFETs. Also, the self-heating can be well controlled in our proposed SDT FinFET which is a difficult task for SOI family. The proposed FinFET is also compared with the existing experimental data, showing that the SDT FinFET not only demonstrates desired short-channel characteristics due to its inherent structure advantages (partially insulating oxide under the channel region), but also reduces the costs of device fabrication due to its simple process method and planar-like structure.

Thermal characteristics of an advanced bMPI-based 1T-DRAM cell

In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.

A novel self-align double gate MOSFET with source/drain tie

In this paper, a novel device architecture, namely novel self-align double gate MOSFET with source/drain tie, is proposed and compared with the ITRS. According to the simulation results, our proposed transistor not only enhances the on/off current ratio, but also decreases the drain induced barrier lowering and subthreshold swing due to the double gate scheme structure.

Design, simulation, and fabrication of a new poly-Si based capacitor-less 1T-DRAM cell

In this paper, we propose a new fabrication method to form a polysilicon thin-film transistor with a smiling SiO2 layer. The experimental results suggest that the short-channel effects can be significantly reduced because the trench oxide is utilized to block the drain electric field. Furthermore, the so-called S/D tie can help to overcome the self-hating for enhancing the thermal reliability. And the device fabrication process is fully compatible with current conventional CMOS technology.

A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.