Hyun-Jae Kang

Study of process contributions to total overlay error budget for sub-60-nm memory devices

According to the 2006 International Technology Roadmap for Semiconductors, the overlay budget of 60nm memory devices is 11nm. To meet such a tight requirement, the total overlay error budget should be controlled carefully. There are many ways to analyze overlay budget; here, however, a simple but accurate methodology is introduced. In this study, total overlay error budget consists of four major contribution categories: scanner, process, metrology, and mask contributions. Scanner contributions are evaluated by measuring machine-to-machine overlay errors in the conventional way. Process contributions are estimated by inverse reactive-ion etch (RIE) lag and chemical mechanical polishing (CMP) erosion. Metrology contributions are evaluated by overlay metrology tools. Finally, mask contributions represent mask-to-mask misregistration. By applying this methodology to 60nm memory devices, it turns out that process contributions are more than 30% of the total overlay error budget for a contact layer. In this art...

Flare in Microlithographic Exposure Tools

To achieve the high level in photolithographic technology that is needed for current microelectronic devices, it is strongly required to consider emerging key parameters that were not critical drawbacks in previous photolithographic techniques. Flare existing in optical elements is one example of such emerging key parameters. In this paper, undesirable linewidth variation due to flare and a measurement method of flare are described. Various phenomena related to linewidth variation due to flare are experimentally observed and theoretically analyzed. Finally, the photomask linewidth correction is introduced to compensate this undesirable linewidth variation due to flare.

Stacked FRAM capacitor etching process for high density application

Abstract In this paper, one step ferroelectric capacitor etching technology has been developed. Stacked capacitor layers with 0.75μm height were etched with a TiN hard mask. Etch selectivity increases as oxygen ratio in capacitor etching gases increases. After etching the electrodes and the PZT film, the slope of the stack capacitor was around 72 degrees and it has been proven that no si dew all fence was generated during the capacitor etching process and its leakage current was below 10–6A/cm2. The 0.9×0.9μm2 area capacitor for a 16M FRAM density has been well fabricated by one step etching process with very high selectivity to the mask.

Statistical approach to design DRAM bitcell considering overlay errors

Overlay performance and control requirements have become crucial for achieving high yield and reducing rework process. Increasing discrepancy between hardware solutions and overlay requirements, especially in sub-40nm dynamic random access memory (DRAM) devices, motivates us to study process budgeting techniques and reasonable validation methods. In this paper, we introduce a SMEM (Statistical process Margin Estimation Method) to design the DRAM cell architecture which considers critical dimension (CD) and overlay variations in the perspectives of both cell architecture and manufacturability. We also proposed the method to determine overlay specifications. Using the methodologies, we obtained successfully optimized sub-40 DRAM cells which accurately estimated process tolerances and determined overlay specifications for all layers.

Overlay metrology for dark hard mask process: simulation and experiment study

Simulation and experimental study results are reported to solve align/overlay problem in dark hard mask process in lithography. For simulation part, an in-house simulator, which is based on rigorous coupled wave analysis and Fourier optics method of high NA imaging, is used. According to the simulation and experiment study, image quality of alignment and overlay marks can be optimized by choosing hard mask and sub-film thickness carefully for a given process condition. In addition, it is important to keep the specification of film thickness uniformity within a certain limit. Simulation results are confirmed by experiment using the state of art memory process in Samsung semiconductor R&D facility.

Study for Evaluation of Surface Cracks on Tribological Coatings Failure in Contacting Systems

The use of linear and second order stress extrapolation to obtain KI and KII in two-dimensional finite element models of a thick plate containing an edge crack was examined. Three loading cases were studied, including classical Mode I and Mode II problems and a problem of tribological contact. Linear extrapolation was observed to yield accurate predictions of KI in cases of dominant Mode I loading. In Mode II situations, notably where the crack faces experienced compressive normal stresses, second order extrapolation was observed to improve estimates of KII

Challenge for effective OCV control in 90-nm logic gate using ArF lithography

The introduction of ArF lithography technology is needed for on-chip linewidth variation(OCV) control less than 10nm in 90nm logic transistor development. Since conventional KrF lithography increased the burdens of mask fabrication and photo process due to excessive optical proximity correction(OPC), ArF lithography is more required to improve pattern feasibility in terms of line edge roughness(LER), corner rounding and contact overlapping margin than before. In this paper, we investigated two major components of OCV, that is, proximity and uniformity using ArF lithography. For a tighter CD control, the proximity can be corrected by hybrid OPC method, which is a combination of rule-based and model-based OPC. The uniformity can be effectively improved by several methods such as lithography-friendly layout formation, optimal substrate condition, decrease in MEEF and tuning of the resist process. In conclusion, by using ArF lithography we could obtain the satisfactory OCV control less than 10nm and reasonable process latitude simultaneously for 90nm logic gate under the condition of well-controlled proximity and uniformity.

One step forward to maturity of AF (assistant feature)-OPC in 100-nm level DRAM application

For 100nm-level patterning using optical lithography, high NA system and various RETs such as PSM, off-axis illumination and OPC are obviously required. In particular, assistant feature (AF)-OPC is indispensable to overcome narrow depth of focus (DOF) caused by iso-dense bias and to compensate for linearity difference under the given OAI condition. Previously we reported the application of AF-OPC in DRAM process with 120nm design rule. The extraction of OPC rule and the feasibility of AF-OPC were successfully confirmed by experimental method in real process. In this paper, more comprehensive and aggressive AF-OPC rule is investigated. The old rule is modified in order to obtain larger common DOF. TO avoid dead zone that means discontinuity between dense line and semi-dense line, we apply a comprehensive rule such as insertion of AF between the neighboring main patterns as many as possible. As a result, the discontinuity of OPC application, which is used with or without AF in the boundary region, is effectively minimized. Also, polygon-shaped AF is used to improve DOF of special main pattern. And then, the mask specification and the behavior of isolated line pattern are predicted in case of very high NA KrF and ArF lithography by simulation result. Considering 100nm design rule, the decrease of common DOF is expected to be severer than now. Finally, the optimum AF-OPC rules such as AF size, space and shape are available and shown in case of very high NA KrF and ArF lithography.