Ikuo Ogoh

Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

A newly developed gate/n/sup -/ overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current. >

Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM

Improved circuits for a 4-Mb CMOS DRAM are described. In one of them, called the effective one-shot gate address buffer, the input address is provided to the gate of a transistor, and a gating transistor located between the input node of the buffer and the transistor is controlled by an equivalent one-shot pulse with sufficient high level. This reduces the row address hold time and also RAS-bar access time. A standby current limitation circuit eliminates the standby current at the input stage of the buffer even with TTL-level input voltage. Test-mode hidden refresh is achieved without test-mode resetting, which enhances the testability and relaxes the test sequence. The RAM employs a 0.8- mu m twin-well CMOS process technology and a stacked capacitor with a storage capacitance of 35 fF. A 58-ns RAS-bar access time and a 65-mA active current at 160-ns cycle are achieved in a die size of a 6.84 mm*14.95 mm. The RAM is housed in a 350-mil small-outline J-leaded package and a 400-mil zig-zag in-line package. >

A 58 ns 4 Mb CMOS DRAM with an effective one-shot gate address buffer

A 4-Mb CMOS dynamic RAM (DRAM) with an effective one-shot gate address buffer has been fabricated. The buffer greatly reduces row address hold time, which gives a fast RAS (row-address strobe) access time of 58 ns. The RAM also implements a novel standby current limitation circuit, which saves the current in the first stage of the buffer even with the TTL-level input voltage. The memory cell has a stacked capacitor. The RAM measures 6.84 mm*14.95 mm and is housed in a 350-mil small-outline J-leaded (SOJ) package and a 400-mil zig-zag in-line package (ZIP).<<ETX>>