John R. Alvis

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Improved CMOS field isolation using germanium/boron implantation

A novel germanium/boron implantation technique for improving the electrical field isolation of high-density CMOS circuits is demonstrated. Germanium implantation causes a reduction in dopant diffusion and segregation during field oxidation and is shown to increase the p-well field threshold voltage by as much as 40% with no significant degradation to junction or device performance. Selective germanium implantation with a blanket boron field implant can also improve the electrical field isolation behavior for CMOS circuits.<<ETX>>

Gain-enhanced LDD NMOS device using cesium implantation

A gain-enhanced LDD NMOS device has been developed for a submicrometer CMOS technology. Using cesium implantation to create a fixed positive charge at the oxide/silicon interface above the LDD region, improvements in device gain are obtained without degradation to hot-carrier reliability or short-channel behavior. Since fixed charge rather than an extended polysilicon gate is used to overlap the LDD regions, no penalty is paid in terms of extra gate overlap capacitance. Furthermore, this structure is easily integrated into a conventional twin-tub CMOS process with the addition of only one cesium implantation step which is performed at the same time as the LDD n/sup -/ implant step. >

Using optical pattern filtering defect inspection tools and process induced defects per wafer pass for process defect control

A patterned wafer inspection system using optical pattern filtering (OPF) has been integrated into sub-half micron semiconductor device pilot production lines (125 mm and 200 mm) for the purpose of process defect control. The optical pattern filtering tool offers the advantages of 0.2 micrometer or better sensitivity with high throughput as compared to other patterned wafer inspection systems, and offers exceptional ability to find defects located deep inside the patterns of a typical device. This three dimensional capability offers unique capability when inspecting contacts or vias. A highly repetitive pattern must be used with the OPF tool. However, this limitation is easily overcome by using large highly repetitive arrays such as those found on DRAM or SRAM technologies. Additionally, the use of specially designed highly repetitive defect array masks such as a diffraction grating (comb) or a series of highly repetitive holes (vias and contacts) can be used.

A novel 0.5- mu m n/sup +/-p/sup +/ poly-gated salicide CMOS process

A novel salicided twin-tub 0.5- mu m CMOS process using germanium implantation is presented. n/sup +/ and p/sup +/ dopants are implanted after salicide formation to fabricate devices with low junction leakage and low silicide-to-diffusion contact resistance. Germanium implantation prior to silicide formation is used to control short-channel transistor characteristics. A significant reduction in the lateral n/sup -/ and p/sup -/ diffusion is observed for germanium-implanted LDD (lightly doped drain) MOSFETs, resulting in minimized overlap capacitance as well as improved short-channel behavior. >

A novel CMOS VLSI isolation technology using selective chlorine implantation

An isolation technology that uses blanket boron and selective chlorine n-well implantation prior to field oxidation is proposed. Chlorine implantation results in an increase in the thermal-oxidation linear-reaction-rate coefficient by a factor of 11.5, which enhances the segregation of dopant atoms in the n-well field region. Due to the redistribution of dopant atoms in the n-well field region, the field threshold voltage magnitude may be increased by as much as 20 V when chlorine implantation is used.<<ETX>>