Nicolas Jourdan

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

Leakage Control in 0.4-nm EOT Ru/SrTiO x /Ru Metal-Insulator-Metal Capacitors: Process Implications

Leakage currents as low as 10^-7 A/cm² at both 1 V and -1 V top electrode bias in the sub-0.4-nm equivalent SiO₂ thickness range are demonstrated in Ru/SrTiO_x/Ru metal- insulator-metal capacitors in which the 8.5-nm SrTiO_x layer is deposited by atomic layer deposition. The top electrode material and deposition technique as well as the postdeposition anneal are crucial parameters to control the leakage, not only at negative, but also at positive top electrode bias.

Evaluation of Metallization Options for Advanced Cu Interconnects Application

The traditional Cu interconnect barrier/seed process consisting of PVD-Ta based barrier/Cu-seed will reach its limit between 20 nm and 30 nm wide trench dimension. To extend Cu interconnect technology further, possible solutions such as PVD-RuTa, PEALD-Ru-based, CVD-Co, PVD/CVD-self-formed-MnSixOy and self-assembled monolayers (SAMs) are studied. It is shown that both PVD-RuTa and CVD-Co possess the so-called seed enhancement capability allowing Cu filling of narrow recesses. However, they exhibit limitations in terms of Cu-diffusion barrier efficiency, electromigration reliability and scalability. Despite, the concept of SAM [NH2-SAM(C3)] as Cu diffusion barrier is demonstrated, it requires maturity and compatibility within the process flow (e.g. adhesion with the Cu overlayer). Finally, it is considered that PEALD-Ru-based alloys and CVD-based MnSixOy films are serious candidates for sub-30 nm wide trench technologies because of their conformal nature and ability to act as an efficient Cu diffusion barrier in the range of 2 nm thickness.

Through-silicon via technology for three-dimensional integrated circuit manufacturing

Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.

Reliability study on cobalt and ruthenium as alternative metals for advanced interconnects

Cobalt and ruthenium are being proposed to replace copper in BEOL interconnects. Using intrinsic TDDB studies, we show that Co needs a barrier to prevent it from drifting into SiO2, where for Ru no drift into any of the three studied dielectrics is observed. Although our intrinsic EM studies on single damascene lines filled with Co suffered from bondpad delamination and a non-optimized CMP, we could still conclude that the EM-performance is better compared to Cu filled lines, where a much better performance of Ru filled lines is demonstrated (>25x). Via failures on Ru schemes show a >5x higher lifetime compared to Cu schemes.

Semi-empirical interconnect resistance model for advanced technology nodes: A model apt for materials selection based upon test line resistance measurements

A semi-empirical interconnect resistance model apt for fitting wire resistance data is presented. The model combines grain boundary and sidewall scattering effects with the impact of Line Edge Roughness (LER). After calibration onto experimental meander-fork structure resistance measurements, extrapolation of the model to future technology nodes reveals that for ultra-narrow line widths a better LER control will be imperative. The model is also intended for inclusion of more accurate, geometry dependent interconnect and via resistance estimators in higher abstraction level simulators, enabling a more realistic assessment of the impact of BEOL parasitics on circuit delay and power at advanced technology nodes.

CVD-Mn/CVD-Ru-based barrier/liner solution for advanced BEOL Cu/Low-k interconnects

Aggressive downscaling of the barrier/liner thickness is the key to meet line and via resistance requirements from 15nm metal half pitch and below interconnects. For this purpose, porous low-k(2.4) dielectric/Mn-based barrier/Ru-liner/Cu system was extensively studied. Mn-silicate (MnSiO3) formation, intrinsic Cu diffusion barrier property and O2 barrier efficiency of the system were demonstrated. A stack of 1nm Mn-based barrier/1nm Ru liner was successfully integrated in tight pitch dual damascene (DD) Cu wires and its extendibility to at least 15nm feature size was confirmed both morphologically and electrically. Although, it was shown that Mn/Ru-based system is intrinsically reliable from electro-migration (EM) perspective, the absence of the flux divergence at the via bottom was also established, which needs to be addressed. Overall, this work shows that the Mn/Ru-based system is a serious barrier/liner solution for future technology nodes.

N5 technology node dual-damascene interconnects enabled using multi patterning

We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut (block), and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.