Jiahui Yuan

On the Performance Limits of Cryogenically Operated SiGe HBTs and Its Relation to Scaling for Terahertz Speeds

The goal of achieving terahertz (THz) transistors within the silicon material system has generated significant recent interest. In this paper, we use operating temperature as an effective way of gaining a better understanding of the performance limits of SiGe HBTs and their ultimate capabilities for achieving THz speeds. Different approaches for vertical profile scaling and reduction of parasitics are addressed, and three prototype fourth-generation SiGe HBTs are compared and evaluated down to deep cryogenic temperatures, using both dc and ac measurements. A record peak fT/fmax of 463/618 GHz was achieved at 4.5 K using 130-nm lithography (309/343 GHz at 300 K), demonstrating the feasibility of reaching half-THz fT and fmax simultaneously in a silicon-based transistor. The BVCEO of this cooled SiGe HBT was 1.6 V at 4.5 K (BVCBO = 5.6 V), yielding a record fT times BVCEO product of 750 GHzldrV (510 GHzldrV at 300 K). These remarkable levels of transistor performance and the associated interesting device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. It is predicted in a new scaling roadmap that fT/fmax of room-temperature SiGe HBTs could potentially achieve 782/910 GHz at a BVCEO of 1.1 V at the 32-nm lithographic node.

On the Frequency Limits of SiGe HBTs for TeraHertz Applications

We report record f_max for a silicon-based transistor, and the first combined set of f₁+ f_max above one-terahertz for silicon-germanium heterojunction bipolar transistors (SiGe HBTs). Peak f_max of 618 GHz and f_rfloor of 463 GHz at 4.5 K (chuck temperature) were measured for a scaled 0.12 times 2.5 mum-SiGe HBT (343 / 309 GHz at 300 K), at a breakdown voltage BV_CEO of 1.62 V (1.70 at 300 K), yielding a record f_T x BV_CEO product of 750 GHz-V (510 GHz-V at 300 K). An examination of base transport in these devices at low temperatures suggests non-equilibrium effects are operative.

Impact of Scaling on the Inverse-Mode Operation of SiGe HBTs

The inverse-mode operational regime of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) has to date been largely ignored and is typically dismissed as a viable possibility for circuit applications due to the general perception of its limited dc and ac performance capabilities. In this paper, the inverse-mode performance of four distinct generations of SiGe HBTs is investigated and is found to improve impressively with generational scaling. The physics behind these scaling-induced improvements is examined in detail using a combination of measurements and calibrated simulations. A novel lateral dependence of the inverse-mode base current is identified and is shown to potentially present new opportunities for even larger improvements in inverse-mode performance in SiGe HBTs. A record peak fT in inverse mode of 25 GHz is reported for a prototype fourth-generation device

Design and Optimization of Superjunction Collectors for Use in High-Speed SiGe HBTs

After reviewing the various mechanisms causing breakdown in bipolar transistors, we present a novel collector design for silicon-germanium heterojunction bipolar transistors (SiGe HBTs). The design improves the well-known speed/breakdown voltage tradeoff in SiGe HBTs for radio-frequency (RF) and millimeter-wave applications. Applying multiple alternating p- and n-type layers (a superjunction) deep in the collector-base (CB) space-charge region (SCR) alters the electric field and electron temperature in the CB junction. Consequently, impact ionization is suppressed, whereas the width of the CB SCR is not increased, and therefore, the breakdown voltages BVCEO and BVCEO are increased, with no degradation in the device speed or RF performance. For a fixed alternating-current performance, BVCEO is improved by 0.33 V, producing a SiGe HBT with fT = 101 GHz, fmax = 351 GHz, and BVCEO = 3.0 V, as predicted by calibrated DESSIS technology computer-aided design simulations. Concerns with regard to the influence of thermal cycles associated with fabrication are considered, and a more practical doping profile is proposed to simplify the use of superjunctions. The proposed structure is also contrasted with other approaches from the literature.

An Investigation of Negative Differential Resistance and Novel Collector–Current Kink Effects in SiGe HBTs Operating at Cryogenic Temperatures

In this paper, a new negative-differential-resistance (NDR) effect and a novel collector-current kink effect are investigated in the cryogenically operated SiGe heterojunction bipolar transistors (HBTs). Theory based on an enhanced positive-feedback mechanism associated with heterojunction barrier effect at deep cryogenic temperatures is proposed to explain both the observed NDR and the collector-current kink. The accumulated charge induced by the barrier effect acts at low temperatures to enhance the total collector-current, indirectly producing both phenomena. This theory is confirmed using the calibrated 2-D DESSIS simulations over temperature. These unique cryogenic effects also have significant impact on the ac performance of SiGe HBTs operating at high injection. Technology evolution plays an important role in determining the magnitude of the observed phenomena, and the scaling implications are addressed. In addition, the present NDR effect is also compared with previously reported NDR and hysteresis effects observed in highly scaled SiGe HBTs operating under forced-IB-base bias. The input drive condition of the transistor during its use in circuits, either under pure forced-current bias or under pure forced-voltage bias, or more practically, somewhere in between, determines the magnitude of the observed NDR and is of potential concern for circuit designers and must be carefully modeled

Enhancing the Speed of SiGe HBTs Using fT-Doubler Techniques

A peak f_T of 325 GHz is achieved, for the first time, in a 130 nm, 200 GHz, 3^rd-generation SiGe HBT technology at 300 K, by utilizing f_T-doubler techniques. This speed enhancement is equivalent to gaining an additional generational node (from 3^rd to 4^th), with no underlying change to the transistor profile or lithography. The f_T-doubler can be treated as a single transistor unit cell during circuit design, which is verified by the investigation of its small-signal equivalent circuit. Reduced C_pi is demonstrated to be the root origin of the f_T-enhancement. The impact of emitter geometry on performance is investigated. A record f_T of 438 GHz is achieved at 93 K.

A 10 Mbps SiGe BiCMOS Transceiver for Operation Down to Cryogenic Temperatures

A 10 Mbps wire-line transceiver compatible with the RS-485 standard is implemented in SiGe BiCMOS technology. This general purpose SiGe bus transceiver represents the first demonstration of a wide temperature range (-180degC to +27degC) enabled, radiation tolerant as built, wire-line transceiver, and is intended for use in emerging space system avionics platforms. Robust functionality within specifications from -180degC to +27degC is demonstrated.

SiGe HBT CML Ring Oscillator With 2.3-ps Gate Delay at Cryogenic Temperatures

We present a measured current-mode logic ring oscillator gate delay of 2.3 ps, a record for digital circuits in silicon-based technologies. This result was achieved in a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology operating at 25 K. In addition to higher cutoff frequency and lower collector-base capacitance, lower base resistance is also responsible for the improved switching speed at cryogenic temperatures. The self-heating characteristics of these SiGe HBT circuits are also investigated across temperatures.

An investigation of collector-base transport in SiGe HBTs designed for half-Terahertz speeds

A new method is introduced to investigate electron transport in the collector-base space charge region of SiGe HBTs designed for half-Terahertz speeds. Using commercially-available Monte Carlo and hydrodynamic TCAD tools, one can eliminate the fundamental limitations of hydrodynamic models related to velocity overshoot and impact ionization. The method is verified in a 200-GHz SiGe technology and then applied to hypothetical 350-GHz and half-THz (500 GHz) SiGe HBTs. This new approach requires far less computational complexity than classical Monte Carlo tools.

Improved 2-D regional transit time analysis for optimized scaling of SiGe HBTs

A new method for two-dimensional (2-D) regional transit time analysis in SiGe HBTs is presented, using a commercially-available TCAD suite with hydrodynamic device simulations. The quasi-static 2-D transit time analysis is first used to determine the cutoff frequency of a well-calibrated 200 GHz SiGe HBT and then applied to the design of hypothetical SiGe HBTs with peak cutoff frequencies of 375 GHz and 450 GHz. These results are benchmarked against full frequency-domain simulations. The new regional analysis is then demonstrated at each scaling node and used to illuminate the 2-D nature of the onset of the Kirk effect and heterojunction barrier effect. These techniques enable the cutoff frequency and transit time components to be determined at lower computational complexity and in greater detail than traditional frequency-domain simulations, and are very useful for optimized scaling.