Xuanwu Kang

CMOS Process-Compatible High-Power Low-Leakage AlGaN/GaN MISHEMT on Silicon

We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded Si₃N₄/Al₂O₃ bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance <i>R</i>_{on, sp} of 2.9 mΩ·cm². The off-state drain leakage at 600 V is 7 μA. We show robust gate dielectrics with a large gate bias swing.

AlGaN/GaN/AlGaN Double Heterostructures Grown on 200 mm Silicon (111) Substrates with High Electron Mobility

In this work, we demonstrate, for the first time, Al0.35GaN/GaN/Al0.25GaN double heterostructure field effect transistors on 200 mm Si(111) substrates. Thick crack-free Al0.25GaN buffer layers are achieved by optimizing Al0.75GaN/Al0.5GaN intermediate layers and AlN nucleation layers. The highest buffer breakdown voltage reaches 1380 V on a sample with a total buffer thickness of 4.6 µm. According to Van der Pauw Hall measurements, the electron mobility is 1766 cm2 V-1 s-1 and the electron density is 1.16×1013 cm-2, which results in a very low sheet resistance of 306±8 Ω/square.

Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates

Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates u sing a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc.. An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator, and yielded fully functional power devices.

Fabrication and Performance of Au-Free AlGaN/GaN-on-Silicon Power Devices With

Au-free GaN-based metal-insulator-semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al₂O₃-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si₃N₄ and Al₂O₃. The Si₃N₄ layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al₂O₃ layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600 V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <;1 Ω·mm. The devices show high maximum output current density (>0.4 A/mm); and low gate and drain leakage (<;10^-10 A/mm). The maximum pulsed mode drain-source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m Ω·cm².

{\rm Al}_{2}{\rm O}_{3}

We describe the fabrication and characteristics of high voltage enhancement mode SiN/AlGaN/GaN/AlGaN double heterostructure FET devices. The Si3N4 not only acts as a passivation layer but is crucial in the device concept as it acts as an electron donating layer (1). By selective removal under the gate of the in-situ SiN, we realize e-mode operation with a very narrow threshold voltage distribution with an average value of +475 mV and a standard deviation of only 15 mV. Compared to the reference depletion mode devices, we see no impact of the e-mode architecture on the breakdown behaviour. The devices maintain very low leakage currents even at drain biases up to 80% of the breakdown voltage.

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We report on the first measurement results to obtain over 2 kV breakdown voltage (VBD) of GaN-DHFETs on Si substrates by etching a Si Trench Around Drain contacts (STAD). Similar devices without trenches show VBD of only 650 V. DHFETs fabricated with STAD technology show excellent thermal performance confirmed by electrical measurements and finite element thermal simulations. We observe lower buffer leakage at high temperature (100°C) after STAD compared to devices with Si substrate, enabling high temperature device operation.

{\rm Si}_{3}{\rm N}_{4}/{\rm Al}_{2}{\rm O}_{3}

We find that off-state breakdown in AlGaN/GaN insulated-gate HEMTs can occur at the source-side of the gate with increase in the drain voltage. This new finding is borne out by extensive electrical measurements and confirmed with the OBIRCH (Optical Beam Induced Resistance CHange) technique. It is explained by a hypothesis whereby holes generated at high Vds flow to the source-side of the gate, and due to the low valence band offset, enter the gate insulator and damage it. Holes also cause threshold voltage shifts that turn the device on. The damage occurs in discrete spots, as would be expected by defects. Finally, we show improved breakdown voltage with a better gate-dielectric interface.

Gate Dielectrics

The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (VTH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the VTH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (Dit) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150°C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nm-thick PE-ALD SiN gate dielectric.

Low leakage high breakdown e-mode GaN DHFET on Si by selective removal of in-situ grown Si 3 N 4

In this work we report on the two most common failure modes for AlGaN/GaN-based HEMTs: the gate leakage increase and the output current drop. First, by performing step-stress experiments in function of the step-time (tSTEP) we show that the critical voltage for the increase of gate leakage current depends on the tSTEP and is not associated with a permanent drop of the output current. Consequently, identification of the critical voltage by means of step-stress is not meaningful per se since it depends on the tSTEP used. Second, we show that during high power stress at high voltage a permanent output current drop occurs. The failure analysis reveals the formation of crystallographic defects in the AlGaN layer along the whole width of the gate, in agreement with the inverse piezoelectric theory. However, in contrast to the degradation model based on the inverse piezoelectric effect, these defects do not aid the leakage of electrons from the gate toward the drain electrode since the output current drop is not associated with an increase of the gate leakage current. Therefore, combining the outcome of the two experiments, we suggest that the two most common failure modes are not correlated despite both might concur to the device degradation. Finally, an excellent stability is shown for devices with reduced Al content in the AlGaN barrier, highlighting the fundamental role of strain on reliability of AlGaN/GaN-based devices.

Si Trench Around Drain (STAD) technology of GaN-DHFETs on Si substrate for boosting power performance

The p-GaN gate HEMT device architecture is a prime contender for normally-off GaN power transistors. In this work the growth parameters of the Mg doped p-type GaN layer are varied and the impact of Mg out-diffusion and Mg activation on the main HEMT device parameters is studied. The Mg chemical concentration is optimized together with the Mg active concentration to obtain improved device performance. Enhancement mode 36 mm p-GaN gate power transistors have been realized, featuring a threshold voltage of 2.1 V and a Ron of 150 ma.