Soon Aik Chew

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Highly scalable bulk FinFET Devices with Multi-V T options by conductive metal gate stack tuning for the 10-nm node and beyond

A scalable multi-VT enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-VT is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack Tinv, JG, DIT and reliability as well as the device performance are shown to be unaffected by the multi VT process.

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (Vt, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

Implementing cubic-phase HfO 2 with κ-value ∼ 30 in low-V T replacement gate pMOS devices for improved EOT-Scaling and reliability

Higher κ-value HfO₂ (κ~30) was evaluated in replacement metal gate pMOS devices. The higher-κ was achieved by doping and anneal of the HfO₂ causing crystallization into the cubic phase. The resulting gate-stack has up to 10³ × lower gate-leakage current compared to a reference HfO₂: J_G at -1 V ~ 2 μA/cm² at EOT~9.7 Å. The better J_G - EOT-scaling, result in performance and reliability improvements when normalized to the J_G.

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10-10 A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.

Improved sidewall doping of extensions by AsH 3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk FinFETs

We demonstrate a novel photoresist-compatible FinFET doping technique that combines the advantages of deposition and implantation. Energy and deposition thickness optimization for the Ion Assisted Deposition and Doping (IADD) process provides excellent doping of nMOS extensions, thus reducing external resistance REXT. On current ION is improved by 6-8% for LG of 26-30 nm and by 15% for LG of 20 nm, with better SCE and DIBL.

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm^-3) was used as a diffusion source. SiO₂ cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO₂ exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the high etch rate of the PSG/SiO₂ cap stack after drive-in anneal, the PSG/SiO₂ cap was successfully removed by HF with minimum removal of STI and gate hard mask oxide. PSG provides damage free and uniform sidewall doping to fin. On current I_ON is improved by 20% for L_G in the 30-24 nm range, with similar I_OFF and better DIBL compared to P ion implanted reference.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Process control & integration options of RMG technology for aggressively scaled devices

We report on aggressively scaled RMG-HKL devices, with tight low-V_T distributions [σ(V_Tsat) ~ 29mV (PMOS), ~ 49mV (NMOS) at L_gate~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced H_gate, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight R_gate distributions down to L_gate~20nm, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (H_gate~60nm, L_gate≥30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO₂ post-deposition N₂-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.