Karsten Wieczorek

Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length

This letter demonstrates that the conventional two-element lumped model can provide valid capacitance-voltage (C-V ) characteristics for gate oxides with large tunneling current, if the gate length is reduced. The two-element models generally suffer from severe distortion of C-V due to tunneling current, resulting in poor oxide thickness extraction. The distortion can be suppressed using high frequencies in series model or using short gate lengths in parallel model. Considering instrument limits and manufacturability, however, the parallel model is more desirable. The distortion can be completely suppressed up to 10/sup 4/ A/cm/sup 2/ of tunneling current, using gate lengths shorter than 0.2 /spl mu/m in parallel model.

Tunneling Effective Mass of Electrons in Lightly N-Doped

In this paper, we study the dependence of the tunneling effective mass of electrons on gate dielectric nitrogen concentration and thickness in MOSFETs with lightly doped silicon oxynitride (SiOxNy) gates. The direct tunneling current is modeled by applying a Schrodinger-Poisson solver with one-side-open boundary condition. The dependences of the effective mass on nitrogen concentration and dielectric thickness are extracted by fitting the computation results for the gate leakage current to the experimental data that we measured for samples with different thicknesses and nitrogen concentrations. Nitrogen concentration and thickness of samples are determined using X-ray photoemission spectroscopy. The obtained results show a strong dependence of the effective mass on the sample thicknesses and nitrogen concentration. The electron effective mass is found to increase as the thickness decreases, and the higher nitrogen concentration causes a reduction in effective mass.

\hbox{SiO}_{x} \hbox{N}_{y}

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

Gate Insulators

In the presented work we demonstrate an efficient way to improve the balance between performance and reliability in the case that microprocessor speed is limited by a pMOS dominated speed path. It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the selective control of nMOS and pMOS GOX, pMOS degradation in terms of HCI and NBTI can be effectively reduced at tolerable loss of initial product frequency. Fast Wafer Level Reliability (fWLR) techniques are used as an effective tool to quickly characterize the thickness dependence of the degradation components. Product wearout experiments confirm that less product frequency degradation is observed with a thicker P-TOX, which is in agreement with the degradation of ringoscillator frequency as well, stressed in parallel to the product.

Advanced transistor structures for high performance microprocessors

The leakage current through the oxide of an n-channel metal-oxide-semiconductor (MOS) structure with an open boundary on one side is numerically computed by applying a one-dimensional Schrodinger-Poisson self-consistent solver. By embedding the n-channel MOS structure in a well, which prevents the penetration of particles into the metallic gate, the potential profile, the bounded energy levels, and the spatial distribution of electrons in the quantized levels are calculated in the inversion regime. Penetration of electrons into the metallic gate with an open boundary results in a broadening of the discrete bound states at the interface of the substrate with the oxide, transforming the bounded energy levels to the quasibound states. Starting from the continuity equation, a qualitative formula for the current in terms of the electron lifetime in the quasibound states is derived. Based on the determination of the energy level width corresponding to the wave functions, we suggest a method to compute the lifet...

Reliability Guard Band Reduction by Differential Targeting of pMOS Gate Oxide Thickness

In this work we present a comprehensive comparison of ultra thin thermally nitrided (TN) to plasma nitrided (PN) gate dielectrics (GD). We will show that thermal nitridation is a promising technique to increase the nitrogen concentration up to 25%. Furthermore, we will demonstrate that ultra thin thermally nitrided GD have the potential to be an alternative solution compared to plasma nitrided GD. This work includes the analysis of physical and electrical parameters as well as reliability results from reliability characterization. Additionally, we investigated the impact of Deuterium on electrical parameters and reliability behavior.